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Chromatic Research, Inc. Patents
Assignee:
Chromatic Research, Inc.
Address:
Sunnyvale, CA
No. of patents:
20
Patents:












Patent Number Title Of Patent Date Issued
6002410 Reconfigurable texture cache December 14, 1999
A reconfigurable cache in a signal processor provides a cache optimized for texture mapping. In particular, the reconfigurable cache provides two-banks of memory during one mode of operation and a palettized map under a second mode of operation. In one implementation, the reconfigura
5982373 Dynamic enhancement/reduction of graphical image data resolution November 9, 1999
A method of rendering 3-D graphical image data suitable for use in interactive 3-D applications is provided, which reduces the amount of time required to perform the rendering. This is achieved by dynamically adjusting the resolution of the image depending upon the type of operation
5949439 Computing apparatus and operating method using software queues to improve graphics performance September 7, 1999
A software queue located in an offscreen portion of video memory is used as a large-capacity software queue for queuing messages to a graphics accelerator. Although the software queue is typically stored in a dynamic RAM (DRAM) memory, advantages of faster static RAM (SRAM) are achieved
5864704 Multimedia processor using variable length instructions with opcode specification of source oper January 26, 1999
A media engine is disclosed herein which incorporates into a single chip structure the seven multimedia functions of video, 2D graphics, 3D graphics, audio, FAX/modem, telephony, and video-conferencing. In accordance with the present invention, a media engine includes a signal proces
5859787 Arbitrary-ratio sampling rate converter using approximation by segmented polynomial functions January 12, 1999
A method for resampling includes convolving a given set of samples with the impulse response function of a low-pass filter. In this method, values of the impulse response required for the convolution calculation are computed at the time of resampling from a segmented polynomial approxima
5838968 System and method for dynamic resource management across tasks in real-time operating systems November 17, 1998
A system and method for dynamic resource management across tasks in real-time operating systems is disclosed. The system and method manage an arbitrary set of system resources and globally optimize resource allocation across system tasks in a dynamic fashion, according to a system sp
5834672 Non-linear tone generator November 10, 1998
A method and apparatus for producing a tone (e.g. for music) without use of a waveform memory and using a feedback loop. The feedback loop includes a waveform generator which calculates, in real time, a parabolic approximation to a sine wave. The feedback loop includes a delay phase
5828881 System and method for stack-based processing of multiple real-time audio tasks October 27, 1998
A system and method for stack-based processing of multiple real-time tasks operates on a net list of tasks which operate essentially simultaneously with system resources shared between tasks in a dynamic configuration. This system and method operate to control dispatching of messages whi
5814750 Method for varying the pitch of a musical tone produced through playback of a stored waveform September 29, 1998
A method for resampling includes convolving a given set of samples with the impulse response function of a low-pass filter. In this method, values of the impulse response required for the convolution calculation are computed at the time of resampling from a segmented polynomial approxima
5812437 Programmable logic unit for arithmetic, logic and equality functions September 22, 1998
An arithmetic logic unit is disclosed herein which overcomes problems in the art discussed above. In accordance with the present invention, an ALU includes a plurality of individual programmable logic units which selectively implement arithmetic, logic, and equality comparison operat
5799169 Emulated registers August 25, 1998
A structure and a method allows I/O or memory addresses of hardware registers to be emulated in software by a central processing unit (CPU). In one embodiment, a first-in-first-out (FIFO) memory is provided to queue read and write operations of the emulated hardware registers. A prog
5751622 Structure and method for signed multiplication using large multiplier having two embedded signed May 12, 1998
A signed multiplier circuit which performs selectable multiplication operations on a first word having an upper byte and a lower byte and a second word having an upper byte and a lower byte. A first multiplier means generates a first product representative of the product of the upper
5727211 System and method for fast context switching between tasks March 10, 1998
A system and method for fast context switching between tasks by tracking task utilization of shared system resources and optimizing swapping the shared system resources to backing store by computing the difference between the current task's utilization of the system resources and the
5719802 Adder circuit incorporating byte boundaries February 17, 1998
In accordance with the present invention, an adder is disclosed which combines byte boundary control signals with propagate-generate signal pairs immediately resulting from bit pairs of the input signals. Combining the byte boundary control signals with the first level propagate-generate
5712799 Method and structure for performing motion estimation using reduced precision pixel intensity va January 27, 1998
A method of approximating the pixel intensity values of a current block using the pixel intensity values of a search window, wherein the precision of the number of bits used to represent the pixel intensity values is reduced. The pixel intensity values of the pixels in the current block
5664154 M/A for optimizing retry time upon cache-miss by selecting a delay time according to whether the September 2, 1997
A single dirty bit is maintained in a memory controller for each cache line of a cached memory system using a cache write-back policy. The dirty bit is set after each write access, is reset after each read access in which a cache miss occurs, and is left unchanged after all other memory
5625784 Variable length instructions packed in a fixed length double instruction April 29, 1997
A structure and method for using variable length instructions in an instruction register having a fixed word boundary. The instruction register accommodates a first word and a second word. The first word has a first base instruction and a first flexible instruction aligned with first
5623434 Structure and method of using an arithmetic and logic unit for carry propagation stage of a mult April 22, 1997
A multiplier circuit for use in a system which includes an arithmetic and logic unit (ALU). The multiplier circuit includes a carry save stage which receives a first data value and a second data value, and in response, creates a carry signal and a sum signal. The carry and sum signals ar
5586070 Structure and method for embedding two small multipliers in a larger multiplier December 17, 1996
A multiplier circuit which performs selectable multiplication operations on a first word having an upper byte and a lower byte and a second word having an upper byte and a lower byte. A first multiplier circuit generates a first product representative of the product of the upper bytes
5477543 Structure and method for shifting and reordering a plurality of data bytes December 19, 1995
A shifter circuit and method for simultaneously and independently shifting and reordering a plurality of data bytes. The shifter circuit includes first and second registers which each receive a plurality of data bytes. The first register is coupled to a plurality of first buses, with eac

 
 
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