| Patent Number |
Title Of Patent |
Date Issued |
| 6562638 |
Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout |
May 13, 2003 |
| A method for determining device yield of a semiconductor device design, includes determining statistics of at least one MOSFET parameter from a gate pattern, and calculating device yield from the at least one MOSFET parameter. The method provides a direct simulation link from device layo |
| 6560755 |
Apparatus and methods for modeling and simulating the effect of mismatch in design flows of inte |
May 6, 2003 |
| An exemplary method for simulating the effect of mismatch in design flows comprises receiving measured data, receiving an original model, extracting a mismatch model based on the measured data and the original model, attaching the mismatch model to the netlist to obtain a modified netlis |
| 6557127 |
Method and apparatus for testing multi-port memories |
April 29, 2003 |
| A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports |
| 6543043 |
Inter-region constraint-based router for use in electronic design automation |
April 1, 2003 |
| A system and method for routing wires using an automated circuit design tool includes a process for order negotiation to adjust the ordering of wires back and forth between conduits by considering both inter-region and intra-region constraints on the layout of the wires. Order negotiatio |
| 6543041 |
Method and apparatus for reducing signal integrity and reliability problems in ICS through netli |
April 1, 2003 |
| Described is a method for forming a physical layout on a chip floor for a circuit design based on a netlist. The method tentatively places each of the gates of the netlist to a physical location on the chip floor. The method then estimates potential signal integrity and reliability probl |
| 6543037 |
Delay estimation for restructuring the technology independent circuit |
April 1, 2003 |
| Provided are a method, article of manufacture, and apparatus for estimating delays of networks. An automated design system comprises a computer configured to identify a critical path in a network, calculate a delay for the technology-mapped version of the network, calculate a delay for t |
| 6536023 |
Method and system for hierarchical metal-end, enclosure and exposure checking |
March 18, 2003 |
| An automated design rule checking software system processes a physical layout file of a circuit design to derive a list of vias needing design rule checks for violations in metal end, enclosure and/or exposure design rules. The process involves selection of vias likely to cause design ru |
| 6532271 |
Carrier recovery and doppler frequency estimation |
March 11, 2003 |
| Method and system for carrier recovery and estimation of Doppler shift from a signal source that is moving relative to a signal receiver. A pure carrier preamble for the received signal is processed through each of two stages of a linear predictor to obtain a successively more accurate |
| 6529913 |
Database for electronic design automation applications |
March 4, 2003 |
| A database for storing chip design information comprises a plurality of parallel arrays for storing a particular class of information. The union of related entries commencing at a given array index across the one or more parallel arrays of a particular class forms a structure for a given |
| 6526555 |
Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits us |
February 25, 2003 |
| The present invention introduces methods for implementing gridless non Manhattan architecture for integrated circuits. In one particular embodiment, an integrated circuit layout containing horizontal, vertical, and diagonal interconnect lines is first created. Next, the integrated ci |
| 6519743 |
Method and system for timing and area driven binary and/or matching |
February 11, 2003 |
| A method and system are disclosed for finding the best match from a target library of simple logic cells for a complex logic circuit conception. The inventive method is flexible and can be adapted to several cost functions or criteria. The inventive method finds the best children nodes f |
| 6519609 |
Method and system for matching boolean signatures |
February 11, 2003 |
| A method and system for matching a node of a combinatorial block with a library cell in a technology library using truth tables. A truth table representing the function of the node of the combinatorial block is generated. Similarly, a truth table representing the function of the libr |
| 6516455 |
Partitioning placement method using diagonal cutlines |
February 4, 2003 |
| Some embodiments of the invention are placers that use diagonal lines in calculating the cost of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net list, a bounding box that enclose |
| 6516447 |
Topological global routing for automated IC package interconnect |
February 4, 2003 |
| An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide singular ideal IC package routing solution. Topological Global Routin |
| 6504885 |
System and method for modeling mixed signal RF circuits in a digital signal environment |
January 7, 2003 |
| A behavioral model for mixed signal RF circuits. The model approximates non-linear filtering effects for base-band (i.e. suppressed carrier) end-to-end systems analysis. The new model, the K-model, is a linear MIMO (multi-input-multi-output) model with output radius corrected by a no |
| 6493849 |
Method for determining the steady state behavior of a circuit using an iterative technique |
December 10, 2002 |
| An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a shooting method to form a non-linear system of equations for initial conditions of the circuit that directly result in the periodi |
| 6457159 |
Functional timing analysis for characterization of virtual component blocks |
September 24, 2002 |
| A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for |
| 6452910 |
Bridging apparatus for interconnecting a wireless PAN and a wireless LAN |
September 17, 2002 |
| A Wireless bridge conjoins two previously incompatible technologies within a single device to leverage the strengths of each. The Wireless bridge marries the Personal Area Network (PAN) technology of Bluetooth as described in Bluetooth Specification Version 1.0B with the Wireless Local |
| 6442739 |
System and method for timing abstraction of digital logic circuits |
August 27, 2002 |
| A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits containe |
| 6405345 |
Updating placement during technology mapping |
June 11, 2002 |
| A method for estimating the position of a matched cell takes into account the interconnectivities of that cell, without relying on the location of cells connected to the matched cell. The new method is referred to as the Weighted Center of Mass of Covered method. In this method, weights |
| 6401231 |
Method and apparatus for performing both negative and positive slack time budgeting and for dete |
June 4, 2002 |
| Two time budgeting techniques are provided that are suitable for early and late integrated circuit design phases, respectively. During the early design phase, both the positive and negative slack paths are time budgeted, such that a positive slack path cannot become a negative slack |
| 6400592 |
Content addressable memory cell and design methodology |
June 4, 2002 |
| A CAM cell design methodology and a method of pre-charge and comparison timing is disclosed. A CAM cell utilizing this design methodology includes a P-channel transistor configured to communicate a comparison result to a match line using the Miller effect. In one embodiment, the CAM cell |
| 6397371 |
Procedure for worst-case analysis of discrete systems |
May 28, 2002 |
| A general methodology for worst-case analysis of systems with discrete observable signals is disclosed. According to one embodiment, a signature .sigma. is chosen and a .sigma.-abstraction F is created, based on the system and the particular property to be analyzed. This procedure requir |
| 6385759 |
Method for reducing memory requirements in static timing analysis |
May 7, 2002 |
| A method used inside a static timing analyzer, or any timing-driven tool, to reduce the memory required to store the timing values. A static timing analyzer stores the arrival times and the required times at every pin of a digital circuit design. As circuit density increases, the number |
| 6381563 |
System and method for simulating circuits using inline subcircuits |
April 30, 2002 |
| A system and method for generating inline subcircuits that enable a circuit designer to model and simulate circuits that when compared to conventional system and methods reduces the hierarchy from the perspective of the circuit designer, more efficiently models parasitic components, more |
| 6378116 |
Using budgeted required time during technology mapping |
April 23, 2002 |
| A method for selecting which covers to retain for each node reduces the computational burden for large logic cones and large cell libraries. At each node only K covers are retained. These covers have timing performances which are centered around the ideal timing performance for that |
| 6377091 |
Mechanism for maintaining relatively constant gain in a multi-component apparatus |
April 23, 2002 |
| A gain adjustment circuit for maintaining the overall gain of a multi-component apparatus at a relatively constant level is disclosed. A multi-component apparatus in which the gain adjustment circuit may be implemented includes a first component and a second component. The first comp |
| 6363518 |
Automated positioning of relative instances along a given dimension |
March 26, 2002 |
| A computer-automated tool re-positions an instance relative to another instance along a given dimension. First, positions of both instances along the given dimension are determined. Then, a modified position is determined for one instance according to a convex function, which defines |
| 6351841 |
Method and apparatus for creating multi-gate transistors with integrated circuit polygon compact |
February 26, 2002 |
| A method of creating multi-gate transistors with integrated circuit polygon compactors is disclosed. Specifically, in order to provide a more efficient layout when the size of a transistor is increased during design migration, a small multi-gate transistor is formed by inserting at least |
| 6349272 |
Method and system for modeling time-varying systems and non-linear systems |
February 19, 2002 |
| A method and system for generating reduced models of systems having a time-varying elements, a non-linear elements or both is provided. The system and method can be utilized with any systems that are capable of being described with non-linear or time-varying differential equations. T |
| 6342816 |
Voltage limiting bias circuit for reduction of hot electron degradation effects in MOS cascode c |
January 29, 2002 |
| MOS Cascode amplifier circuits are subject to long-term or instantaneous changes (degradation) of performance characteristics by excess substrate currents. These currents can be generated in the grounded source transistor of the cascode connected output transistors during peak excurs |
| 6331833 |
Highly linear sigma-delta modulator having graceful degradation of signal-to-noise ratio in over |
December 18, 2001 |
| A multi-bit analog-to-digital converter architecture, which during normal operation behaves like a single-bit converter, thus sharing the high linearity and low distortion properties of the simpler system. When a high input signal is applied, a second bit is triggered and the system beha |
| 6314131 |
Method and system for channel estimation using multi-slot averaged interpolation |
November 6, 2001 |
| A method of Multi-slot Averaged Linear Interpolation (MALI) to estimate channel transfer characteristics at a receiver in a wireless network. The method and system are particularly well suited to use in wideband CDMA transmission systems. The steps of the method include calculating an |
| 6308299 |
Method and system for combinational verification having tight integration of verification techni |
October 23, 2001 |
| A method and system for combinational verification tightly integrates multiple verification methods. The present invention performs random simulation on the inputs of two combinational netlists. The nets within the netlists are described as BDDs and divided into classes of cutpoint c |
| 6301578 |
Method of compressing integrated circuit simulation data |
October 9, 2001 |
| A method of compressing a block of time series data involves sorting the data by variable name, separating the series of time values from the series of variable values, and performing data extraction and/or compression independently on the series of time values and on the series of v |
| 6269467 |
Block based design methodology |
July 31, 2001 |
| A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience be |
| 6263478 |
System and method for generating and using stage-based constraints for timing-driven design |
July 17, 2001 |
| An integrated circuit design is divided into partitions which each contain two stages of information. The first stage corresponds to sources within the design, and the second stage corresponds to targets within the design. In one implementation, all of the sources in each partition are t |
| 6263301 |
Method and apparatus for storing and viewing data generated from a computer simulation of an int |
July 17, 2001 |
| A method and apparatus for managing simulation results involves identifying distinct transactions in a group of simulation results so that the simulation results can be stored and viewed on a transaction basis instead of as a single continuous block of simulation results. A transaction i |
| 6247163 |
Method and system of latch mapping for combinational equivalence checking |
June 12, 2001 |
| A method and system of latch mapping for performing combinational equivalence checking on a specification and an implementation of a circuit that does not depend on signal names or circuit structure to determine the latch mapping. First, every latch is mapped to every other latch. Then, |
| 6229289 |
Power converter mode transitioning method and apparatus |
May 8, 2001 |
| A method and apparatus are provided for transitioning a power converter between a switched mode of operation and a linear regulator mode of operation. The power converter operates according to one or more intermediate modes of operation in which the switched mode and linear regulator |
| 6215288 |
Ultra-low power switching regulator method and apparatus |
April 10, 2001 |
| A low-power controller for a discontinuous switched mode power converter. The controller has an inductor current sensing circuit to measure the inductor current flowing through an inductive charge storage element as well as an output voltage sensing circuit to monitor output voltage. The |
| 6181754 |
System and method for modeling mixed signal RF circuits in a digital signal environment |
January 30, 2001 |
| A behavioral model for mixed signal RF circuits. The model approximates non-linear filtering effects for base-band (i.e. suppressed carrier) end-to-end systems analysis. The new model, the K-model, is a linear MIMO (multi-input-multi-output) model with output radius corrected by a no |
| 6163763 |
Method and apparatus for recording and viewing error data generated from a computer simulation o |
December 19, 2000 |
| A method and apparatus for managing simulation results involve identifying errors within a group of simulation results so that the errors can be recorded into a database and viewed for analysis. In a preferred embodiment of the invention, distinct transactions within a group of simul |
| 6161078 |
Efficient method for solving systems of discrete rotation and reflection constraints |
December 12, 2000 |
| A computer implemented, graph based method for determining the orientation of objects which can assume a plurality of orientations relative to a default orientation, including being rotated 90.degree. clockwise, mirrored about an X axis, or mirrored about a Y axis, where the X axis and |
| 6157684 |
One bit matched filter with low complexity and high speed |
December 5, 2000 |
| Described is an one bit matched filter for generating a sequences of correlations between a signal bit stream and a sample stream of n sample bits. The n sample bits are arranged in a rang of n bit positions n, n-1, . . . , 2, 1. Among the n sample bits, m boundary positions are defined |
| 6151698 |
Method for determining the steady state behavior of a circuit using an iterative technique |
November 21, 2000 |
| An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a shooting method to form a non-linear system of equations for initial conditions of the circuit that directly result in the periodi |
| 6124679 |
Discharge lamps and methods for making discharge lamps |
September 26, 2000 |
| In some embodiments, a light bulb for an electrodeless discharge lamp has a protuberance such that the cold spot of the bulb is located in the protuberance. The protuberance is spaced from the induction coil of the lamp so as to be easily accessible. Hence the cold spot temperature is |
| 6107849 |
Automatically compensated charge pump |
August 22, 2000 |
| A charge pump having an automatic compensation capability comprises a current source and a current sink. The current source is selectively coupled to the output of the charge pump by a sourcing control. The sourcing control receives an input control signal and responds by controlling |
| 6102961 |
Method and apparatus for selecting IP Blocks |
August 15, 2000 |
| According to the invention, a method for valuing the contribution of IP Blocks into integrated circuit (IC) designs includes implementing a novel concept for valuing technical and economic factors. Based upon such factors, users can more reliably value, select and use IP Blocks for their |
| 6088523 |
Method and apparatus for simulating an electrical circuit design using approximate circuit eleme |
July 11, 2000 |
| A method and apparatus for making electrical circuits having RLCG lines is disclosed. The method depicts a circuit element taper of a selected element type as dependent upon an accumulated circuit element quantity. The method matches projections of the circuit element taper with proj |
