| Patent Number |
Title Of Patent |
Date Issued |
| 6948138 |
Method for positioning I/O buffers and pads in an IC layout |
September 20, 2005 |
| A method for use by a placement and routing tool automatically selects positions for all n I/O buffers of an IC from among a set of m available legal positions for such buffers within an IC layout so as to best meet a set of criteria affected by I/O buffer placement. The method initially |
| 6944841 |
Method and apparatus for proportionate costing of vias |
September 13, 2005 |
| Some embodiments of the invention provide a method of routing nets in an integrated-circuit layout region that has multiple interconnect layers. The method specifies several routes, where some of the routes utilize vias to traverse multiple interconnect layers. The method assesses a cost |
| 6944838 |
Method and system for design verification using proof-partitioning |
September 13, 2005 |
| A design verifier includes a bounded model checker, a proof partitioner and a fixed-point detector. The bounded model checker verifies a property to a depth K and either finds a counterexample, or generates a proof in the form of a directed acyclic graph. If a counterexample is found, th |
| 6941531 |
Method and apparatus for performing extraction on an integrated circuit design |
September 6, 2005 |
| The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, a complex extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may |
| 6938234 |
Method and apparatus for defining vias |
August 30, 2005 |
| Some embodiments of the invention provide a method of routing nets in a region of a design layout. The region contains a plurality of nets and has multiple interconnect layers. The method identifies routes for a set of nets in the region, where some of the routes utilize vias to traverse |
| 6931616 |
Routing method and apparatus |
August 16, 2005 |
| A routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then |
| 6931615 |
Method and apparatus for identifying a path between source and target states |
August 16, 2005 |
| Some embodiments of the invention provide a path-searching method. This method identifies two sets of states in a multi-state space, where at least some of the states have at least one dimension. It then performs an epsilon-optimal path search to identify an epsilon-optimal path between |
| 6931608 |
Method and apparatus for determining viability of path expansions |
August 16, 2005 |
| For a path search that identifies a path between source and target states in a space, some embodiments of the invention provide a method for determining viability of an expansion of a path from a first state to a second dimensional state. The method computes a first cost function that |
| 6928633 |
IC layout having topological routes |
August 9, 2005 |
| Some embodiments of the invention provide an integrated circuit ("IC") design layout that includes topological routes. This layout includes several nets, each with a set of routable elements in the IC design-layout region. For each net, this layout also includes a topological route that |
| 6928630 |
Timing model extraction by timing graph reduction |
August 9, 2005 |
| Disclosed is a method and system for extracting a timing model. One disclosed approach to extract a timing model is by reducing the timing graph. Original timing behavior is preserved in the timing model including arrival times, slew times, timing violations and even latch time borrowing |
| 6928626 |
System and method for modeling of circuit components |
August 9, 2005 |
| The present invention relates generally to the field of design automation. More particularly, the present invention relates to a system and method for the modeling of circuit components for use by a simulator. The present invention includes a model of a circuit component having a plurali |
| 6925619 |
IC conductor capacitance estimation method |
August 2, 2005 |
| An RC extraction tool estimates capacitances of conductors residing along parallel grid lines on each of a set vertically stacked layers of insulating material of an IC based on data contained in a IC layout file describing positions of structures forming the IC. The tool initially p |
| 6925618 |
Method and apparatus for performing extraction on an integrated circuit design with support vect |
August 2, 2005 |
| The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, a complex extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may |
| 6922800 |
Test sequences generated by automatic test pattern generation and applicable to circuits with em |
July 26, 2005 |
| A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of |
| 6920417 |
Apparatus for modeling IC substrate noise utilizing improved doping profile access key |
July 19, 2005 |
| A method for modeling a substrate, which includes obtaining vertically discretized doping profiles in the substrate to facilitate modeling. The method includes employing substrate region names and substrate cross-section names as access keys to permit accessing of the vertically disc |
| 6918102 |
Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout |
July 12, 2005 |
| A method of determining the position of devices in a circuit layout includes defining an array of cells and defining a plurality of device outlines in the array, with each device outline received in at least one cell. A set of size constraints is established that expresses the size of |
| 6915501 |
LP method and apparatus for identifying routes |
July 5, 2005 |
| Some embodiments provide an LP method that identities routes. In some embodiments, this method is used by a router that defines routes for nets within a region of a design layout. Each net has a set of pins in the region. The method partitions the region into a set or sub-regions. For |
| 6915500 |
Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circu |
July 5, 2005 |
| The present invention introduces several methods for implementing arbitrary angle wiring layers for integrated circuit manufacture with simulated Euclidean wiring. Entire routing layers may be implemented with arbitrary angle preferred wiring using simulated Euclidean wiring. In a first |
| 6915499 |
Method and apparatus for propagating a piecewise linear function to a line |
July 5, 2005 |
| Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a line. In some embodiments, the space includes a set of states and a transition map that specifies a set of states |
| 6915248 |
Method and apparatus for transforming test stimulus |
July 5, 2005 |
| Described is a method for validating a digital design using a simulation process. All possible design states of the design are divided into a plurality of validation regions. In the simulation-process, the method records and updates the simulation history for each of t he validation |
| 6910198 |
Method and apparatus for pre-computing and using placement costs within a partitioned region for |
June 21, 2005 |
| One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then |
| 6907593 |
Method and apparatus for pre-computing attributes of routes |
June 14, 2005 |
| Some embodiments provide a method of pre-computing attributes of routes for nets in a region of a design layout. The pre-computed attributes are used by an electronic design automation application that partitions a design-layout region into a plurality of sub-region. |
| 6907591 |
Method and apparatus for performing extraction using a neural network |
June 14, 2005 |
| A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction mo |
| 6904580 |
Method and apparatus for pre-computing placement costs |
June 7, 2005 |
| Some embodiments of the invention provide a method that pre-computes costs of placing circuit modules in regions of circuit layouts. The method defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a placement operation. For each set of |
| 6901562 |
Adaptable circuit blocks for use in multi-block chip design |
May 31, 2005 |
| Techniques for increasing flexibility in use of virtual component blocks include a method for hardening a foundation block, a pin-unscrambling methodology for semi-hardened virtual component blocks, and parameterizable virtual component blocks. A method for hardening a foundation blo |
| 6900540 |
Simulating diagonal wiring directions using Manhattan directional wires |
May 31, 2005 |
| An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred w |
| 6898773 |
Method and apparatus for producing multi-layer topological routes |
May 24, 2005 |
| Some embodiments of the invention provide a method for identifying topological routes in a multi-layer region of a design layout. The method selects a first net that has several routable elements. For the selected net, it then specifies a first multi-layer topological route that connects |
| 6898772 |
Method and apparatus for defining vias |
May 24, 2005 |
| Some embodiments of the invention provide a method for identifying locations of potential via between two layers of a design layout. The method identifies on one layer a first non-rectangular polygonal region for containing the via, and identifies on the other layer a second non-rect |
| 6895567 |
Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit desi |
May 17, 2005 |
| The present invention introduces several methods for laying out integrated circuit designs that use gridless non Manhattan routing to connect the integrated circuit components. In one embodiment, the non Manhattan routed integrated circuit designs are laid out by creating an initial rout |
| 6892371 |
Method and apparatus for performing geometric routing |
May 10, 2005 |
| Some embodiments of the invention provide a method for generating a route for a net in an integrated circuit ("IC") layout. The method receives a previously defined route. From the received route, it generates several constraining points for specifying a geometric route that is based on |
| 6892369 |
Method and apparatus for costing routes of nets |
May 10, 2005 |
| Some embodiments of the invention provide a method of costing routes for a set of nets. The method identifies at least one route for each net, where each route has a particular length. It also identifies an estimated route length for each net. It then computes a cost that includes an exp |
| 6892366 |
Method and apparatus for performing extraction using a model trained with Bayesian inference via |
May 10, 2005 |
| A system for using machine learning based upon Bayesian inference using a hybrid monte carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The m |
| 6889372 |
Method and apparatus for routing |
May 3, 2005 |
| Some embodiments of the invention provide a method of identifying routes for net in a region of a design layout. The method identifies a first route for a first net without using a routing grid. It then updates at least one previously defined route for another net to account for spacing |
| 6889371 |
Method and apparatus for propagating a function |
May 3, 2005 |
| Some embodiments provide a method of propagating a first function, which is defined over a first state, to a second state in a multi-state space. The method identifies vectors to project from at least some points on the first state that serve as locations of inflection points in the firs |
| 6889326 |
Watermarking based protection of virtual component blocks |
May 3, 2005 |
| A system and method for protecting circuit designs from unauthorized use involves techniques for watermarking by embedding a hidden, recognizable input/output signature or code into the circuit design. An internal sequential function, such as a finite state machine, within the circuit |
| 6889279 |
Pre-stored vector interrupt handling system and method |
May 3, 2005 |
| A pre-stored vector interrupt handling system for rapidly processing interrupt requests from input/output (I/O) devices in processor-based systems includes selection logic and an interrupt vector store to quickly deliver a branch instruction from the interrupt vector store directly to |
| 6887791 |
Optimization methods for on-chip interconnect geometries suitable for ultra deep sub-micron proc |
May 3, 2005 |
| The present invention presents optimization methods for interconnect geometries that readily extend to the UDSM region for determining on-chip interconnect process parameters more realistically and accurately than in the prior art. A method for reconstruction flow that re-assembles each |
| 6886149 |
Method and apparatus for routing sets of nets |
April 26, 2005 |
| Some embodiments of the invention provide a method of routing a set of nets. The method specifies a first order for the set of nets. It then routes the nets according to the specified first order. The method then specifies a second order for the set of nets, where the second order has |
| 6886121 |
Hierarchical test circuit structure for chips with multiple circuit blocks |
April 26, 2005 |
| A hierarchical test control network for an integrated circuit includes a top-level test control circuit block having a chip access port (CAP) controller. The hierarchical test control network also has multiple lower-level test control circuit blocks connected to the top-level test co |
| 6883154 |
LP method and apparatus for identifying route propagations |
April 19, 2005 |
| Some embodiments provide an LP method that identifies route propagations. In some embodiments, this method is used by a router that hierarchically defines routes for nets within a region of a design layout. The router (1) partitions the region into a first set of sub-regions, and (2) for |
| 6883148 |
Method and apparatus for creating an extraction model using Bayesian inference |
April 19, 2005 |
| A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction mo |
| 6882965 |
Method for hierarchical specification of scheduling in system-level simulations |
April 19, 2005 |
| A method for hierarchical specification and modeling of scheduling in system-level simulations. The invention addresses the specification aspect by introducing an explicit notion of a scheduler that must be designed as part of the system. A scheduler effectively represents a scheduling p |
| 6882055 |
Non-rectilinear polygonal vias |
April 19, 2005 |
| Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provi |
| 6880143 |
Method for eliminating via blocking in an IC design |
April 12, 2005 |
| An IC design indicating positions of cells within an IC is processed to determine whether conductors residing above the cells block via access to an input/output (I/O) terminal on an upper surface of any of the cells. Each cell spans several contiguous via spaces in a horizontal directio |
| 6880138 |
Method and apparatus for creating a critical input space spanning set of input points to train a |
April 12, 2005 |
| The present invention introduces novel methods of generating input vectors for machine learning system that will perform extraction. Experimental design is employed to select a set of training points that provide the best information. In one embodiment, a set of input vectors and output |
| 6879934 |
Method and apparatus for estimating distances in a region |
April 12, 2005 |
| Some embodiments of the invention provide a method that computes an estimated distance between an external point and a set of points in a region. This method initially identifies a non-Manhattan polygon that encloses the set of points. It then identifies a distance between the extern |
| 6877149 |
Method and apparatus for pre-computing routes |
April 5, 2005 |
| Some embodiments provide a method of pre-computing routes for nets in a region of a circuit layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. The method then identifies a primary se |
| 6877146 |
Method and apparatus for routing a set of nets |
April 5, 2005 |
| One embodiment of the invention is a method of specifying routes for a group of nets. The method specifies a total cost. It then performs a first depth-first search to identify, for the group of nets, a complete routing solution that has a cost that does not exceed the total cost. A rout |
| 6877143 |
System and method for timing abstraction of digital logic circuits |
April 5, 2005 |
| A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits containe |
| 6877013 |
Methods and apparatus for extracting capacitances exerted on diagonal interconnect lines in an i |
April 5, 2005 |
| Geometric objects, such as polygons, are defined in a multi-dimensional data space, and are represented by data segments. "N" dimensional hierarchical trees, or "ng" trees, are generated to organize the data segments into "outside child nodes" and "inside child nodes" in accordance w |
