| Patent Number |
Title Of Patent |
Date Issued |
| 7013450 |
Method and apparatus for routing |
March 14, 2006 |
| Some embodiments of the invention provide a method of routing several nets in a region of a design layout. Each net includes a set of pins in the region. In some embodiments, the method partitions the region into several sub-regions that have a number of edges between them. The method |
| 7013448 |
Method and apparatus for propagating cost functions |
March 14, 2006 |
| Some embodiments of the invention provide a method of expanding a path in a space with dimensional states. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. The method identifies a f |
| 7013445 |
Post processor for optimizing manhattan integrated circuits placements into non manhattan placem |
March 14, 2006 |
| The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an existing Manhattan based floor planning tool is used. The die size for the floor plan is |
| 7013438 |
System chip synthesis |
March 14, 2006 |
| A technique to design deep sub-micron (DSM) integrated circuits is disclosed, in which global wire delays are minimized first, before performing logic synthesis. According to the present method, a designer performs layout of physical blocks by estimating an area for each block. After |
| 7010784 |
Method and system for split-compiling a hybrid language program |
March 7, 2006 |
| A combined language-compiler that provides for the efficient compilation process of hybrid computer code written using a plurality of computer languages by splitting the hybrid code in such a way that each code statement is optimally independently compilable. The designer specifies b |
| 7010771 |
Method and apparatus for searching for a global path |
March 7, 2006 |
| Some embodiments of the invention provide a method of searching for a global path between first and second sets of routable elements in a region of a layout. The method partitions the region into several rectangular sub-regions. It then identifies a set of sub-regions that contain th |
| 7010767 |
Insertion of repeaters without timing constraints |
March 7, 2006 |
| A method/process for repeater insertion in the absence of timing constraints. Delays are optimized for multi-receiver and multi-layer nets and can be introduced in the early steps of design planning. It serves as a tool for interconnect prediction as well as planning. In the presented |
| 7010765 |
Method for identifying removable inverters in an IC design |
March 7, 2006 |
| An integrated circuit design includes a description of a net for distributing a signal from a root node to one or more leaf nodes downstream of the root node. Some segments of the net include inverters and some segments branch into other segments. The IC design is processed to determ |
| 7010280 |
Linear RF power amplifier and transmitter |
March 7, 2006 |
| A transmitter circuit means is arranged to provide linear amplification of non-constant envelope modulated RF signals by directly amplitude modulating the transmitter power amplifier with the amplitude component of the baseband signal. In addition, the signal to be transmitted is pha |
| 7007270 |
Statistically based estimate of embedded software execution time |
February 28, 2006 |
| A statistical approach to estimating software execution times is implemented by preparing a model of a target processing device, correlating the software to be estimated to benchmark programs used in the preparation of the model, and then applying the software to be estimated to the |
| 7007247 |
Method and mechanism for RTL power optimization |
February 28, 2006 |
| The present invention provides a method and mechanism for optimizing the power consumption of a micro-electronic circuit. According to an embodiment, when optimizing the power consumption of a micro-electronic circuit, one or more candidates for applying one or more optimization tech |
| 7006155 |
Real time programmable chroma keying with shadow generation |
February 28, 2006 |
| A system for forming composite video images from one or more foreground images and one or more background images. In one embodiment, s sum of a suppressed foreground image signal with weight .alpha., with one or more selected foreground colors suppressed, and a background image signal wi |
| 7003754 |
Routing method and apparatus that use of diagonal routes |
February 21, 2006 |
| The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the |
| 7003752 |
Method and apparatus for routing |
February 21, 2006 |
| Some embodiments of the invention provide a method of routing nets in a region of a layout with multiple layers. The method defines a routing graph that has several of nodes on plurality of layers, where each node represents a sub-region on a layer. In the graph, there is a set of edges |
| 7003749 |
Constraint data management for electronic design automation |
February 21, 2006 |
| In a method of determining the existence of one or more conflicts in the placement or configuration of circuit objects defining a circuit, a number of constraints is defined, each of which imposes at least one limitation on at least one circuit object. A number of constraint families |
| 7003748 |
Methods and apparatus for defining Manhattan power grid structures beneficial to diagonal signal |
February 21, 2006 |
| A method for defining and producing a power grid structure of an IC that minimizes the area of the power grid structure area and the diagonal wiring blockage caused by the power grid structure while still meeting design constraints. A power grid planner is used to determine dimensions |
| 7003745 |
Performance modeling for circuit design |
February 21, 2006 |
| Each circuit simulation performed on unique layout of circuit devices generates a design point (DP) that includes device variable values and performance goal values. Circuit models for at least one performance goal are determined as a function of a first subset of the DPs. A performance |
| 7002572 |
Method and apparatus for constructing a convex polygon that encloses a set of points in a region |
February 21, 2006 |
| Some embodiments of the invention provide a method for constructing a convex polygon that encloses a set of points in a region. This method identifies a first polygon that encloses the set of points. It then identifies a second polygon that encloses the set of points. The method then |
| 7000209 |
Method and apparatus for propagating a piecewise linear function to a surface |
February 14, 2006 |
| Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a surface. In some embodiments, the space includes a set of states and a transition map that specifies a set of |
| 6996793 |
Methods and apparatus for storing and manipulating diagonal interconnect lines of a multidimensi |
February 7, 2006 |
| Geometric objects, such as polygons, are defined in a multi-dimensional data space, and are represented by data segments. "N" dimensional hierarchical trees, or "ng" trees, are generated to organize the data segments into "outside child nodes" and "inside child nodes" in accordance w |
| 6996789 |
Method and apparatus for performing an exponential path search |
February 7, 2006 |
| Some embodiments of the invention provide a method of searching for a path. The method identifies a set of source and target elements. It then performs a path search that iteratively identifying path expansions in order to identify a set of associated path expansions that connect the |
| 6990650 |
Method and apparatus for performing technology mapping |
January 24, 2006 |
| Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated paramet |
| 6990647 |
Variable stage ratio buffer insertion for noise optimization in a logic network |
January 24, 2006 |
| A buffer for use in a logic circuit comprises input and output nodes. A first inverter having a first device size is coupled to the input node. A second inverter is coupled in series with the first inverter and with the output node. The second inverter having a second device size at leas |
| 6988257 |
Method and apparatus for routing |
January 17, 2006 |
| Some embodiments of the invention provide a method of defining a global route for a net in a region of a layout, where each net has a set of routable elements. The method partitions the region into several rectangular sub-regions. It then identifies a set of sub-regions that contain |
| 6986117 |
Method and apparatus for identifying a path between source and target states |
January 10, 2006 |
| Some embodiments provide a path-searching method. This method identifies two sets of states in a multi-state space, where at least some of the states have at least one dimension. The method performs a depth-first path search to identify a path between the two sets of states. During the |
| 6983440 |
Shape abstraction mechanism |
January 3, 2006 |
| A method of simulating a design of an electronic system having multiple layers includes, for each layer, storing a plurality of shape occurrences for the layer. A hierarchy of shape instances having a plurality of levels is generated. Each shape instance corresponds to one of the shape |
| 6981235 |
Nearest neighbor mechanism |
December 27, 2005 |
| A method of analyzing a design of an electronic circuit may include selecting a query object in a collection of sets of intervals for the design, where each set of intervals along a first common axis, the collection of sets along a second common axis. Candidate objects within the col |
| 6981233 |
Method for analyzing path delays in an IC clock tree |
December 27, 2005 |
| A macro-cell is incorporated into an integrated circuit (IC) design to describe a fixed arrangement of cells to be included in the IC. The IC includes a clock tree for delivering a clock signal from its root to all clocked devices (sinks) within the IC external to the macro-cell, and to |
| 6980034 |
Adaptive, self-calibrating, low noise output driver |
December 27, 2005 |
| An output buffer includes an output stage that includes a transconductance device configured to drive a capacitive load, and a first capacitor coupled to an input of the transconductance device. A converter converts an input clock signal into a current that is provided to charge the firs |
| 6980006 |
High speed envelope detector and method |
December 27, 2005 |
| Envelope detector and method for determining whether the level of a differential input signal DPIN-DNIN is above a reference voltage V.sub.REF. The differential input signal is converted to a differential current IDP-IDN, the reference voltage is converted to a reference current I.su |
| 6978432 |
Method and apparatus for propagating a piecewise linear function to a point |
December 20, 2005 |
| Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a point. In some embodiments, the space includes a set of states and a transition map that specifies a set of state |
| 6976238 |
Circular vias and interconnect-line ends |
December 13, 2005 |
| Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provi |
| 6976237 |
Method and apparatus for estimating distances in a region |
December 13, 2005 |
| Some embodiments of the invention provide a method that computes an estimated distance between an external point and a set of points in the region. This method identifies a characteristic of the set of points. Based on the identified characteristic, the method then identifies a polyg |
| 6973634 |
IC layouts with at least one layer that has more than one preferred interconnect direction, and |
December 6, 2005 |
| Some embodiments of the invention provide a region of an integrated-circuit ("IC") layout that has a plurality of interconnect layers, where at least one particular layer has more than one preferred interconnect direction. In some of these embodiments, the region has several interconnect |
| 6971076 |
Method for estimating peak crosstalk noise based on separate crosstalk model |
November 29, 2005 |
| Crosstalk noise peaks in output signals of nets of an integrated circuit layout design are estimated by first processing the design to estimate resistances and capacitances of the nets. The design is then processed to identify each aggressor net having at least one section that is proxim |
| 6968524 |
Method and apparatus to optimize an integrated circuit design using transistor folding |
November 22, 2005 |
| A method and system are disclosed to optimize an integrated circuit layout design by determining possible lengths of layout rows that will reduce the total area of the integrated circuit layout (FIG. 4B). The possible row lengths (401B) are determined and stored in a memory unit as a set |
| 6968514 |
Block based design methodology with programmable components |
November 22, 2005 |
| A method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable; collecting data reflecting the experience of the designer regarding the pre-d |
| 6961914 |
Method and apparatus for selecting input points to train a machine learning model for extraction |
November 1, 2005 |
| The present invention introduces novel methods generating training data for machine learning models that will be used for extraction. Specifically, experimental design is employed to select a set of training points that provide the best information. In one embodiment, the training point |
| 6959304 |
Method and apparatus for representing multidimensional data |
October 25, 2005 |
| The invention is directed towards method and apparatus for representing multidimensional data. Some embodiments of the invention provide a two-layered data structure to store multidimensional data tuples that are defined in a multidimensional data space. These embodiments initially d |
| 6957411 |
Gridless IC layout and method and apparatus for generating such a layout |
October 18, 2005 |
| Some embodiments of the invention provide a method of routing nets in a region of an integrated-circuit ("IC") layout. The method selects a net that has several routable elements. It then defines a route for the net. To define the route, the method uses a wiring model that specifies |
| 6957410 |
Method and apparatus for adaptively selecting the wiring model for a design region |
October 18, 2005 |
| Some embodiments provide a method of routing nets in a region of an integrated-circuit layout. This method initially identifies a characteristic of the region, and then selects a wiring model from a set of wiring models, based on the identified characteristic. Each wiring models spec |
| 6957409 |
Method and apparatus for generating topological routes for IC layouts using perturbations |
October 18, 2005 |
| Some embodiments of the invention provide a method for identifying topological routes in a region of an integrated circuit ("IC") design layout. The method receives a set of nets. Each net in the set has a set of routable elements in the IC design-layout region. For each net, the met |
| 6957408 |
Method and apparatus for routing nets in an integrated circuit layout |
October 18, 2005 |
| Some embodiments of the invention provide a method of for routing nets within a region of an integrated circuit ("IC") layout. The method selects a net in the IC layout region. It then identifies a topological route for the selected net. From the selected net's topological route, this me |
| 6957400 |
Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit design |
October 18, 2005 |
| To identify high quality design points in a circuit design, a plurality of design points is generated for the circuit. A subset of the design points is allocated to a design population. A cost is then determined for each allocated design point. From a subset of the allocated design point |
| 6954910 |
Method and apparatus for producing a circuit description of a design |
October 11, 2005 |
| A method is provided for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub |
| 6954908 |
Circuit design point selection method and apparatus |
October 11, 2005 |
| A visualization and data mining technique can be utilized to facilitate analysis of generated sets of design points for an integrated circuit to enable easy and fast understanding of important properties of generated designs. The use of the visualization and data mining technique sig |
| 6952815 |
Probabilistic routing method and apparatus |
October 4, 2005 |
| Some embodiments of the invention provide a method of routing several nets in a region of a design layout. Each net includes a set of pins in the region. In some embodiments, the method partitions the region into several sub-regions that have a number of edges between them. The method (1 |
| 6951006 |
Decomposing IC regions and embedding routes |
September 27, 2005 |
| Some embodiments of the invention provide a method of identifying routes in a region of an integrated circuit ("IC") design layout. The region contains at least one net with several routable elements. The method decomposes the IC design-layout region into a tessellated graph. The tes |
| 6951005 |
Method and apparatus for selecting a route for a net based on the impact on other nets |
September 27, 2005 |
| One embodiment of the invention is a method of routing a group of nets in a region. The method identifies a first route for a first net. It then determines whether embedding the first route in the region will make a set of unrouted nets in the region unroutable. When embedding the first |
| 6948144 |
Method and apparatus for costing a path expansion |
September 20, 2005 |
| Some embodiments of the invention provide a method of propagating a first cost function that is defined over a first state to a second slate in a space representing a design-layout region. In some embodiments, the space includes a set of states and a transition map that specifies a set o |
