| Patent Number |
Title Of Patent |
Date Issued |
| 7216308 |
Method and apparatus for solving an optimization problem in an integrated circuit layout |
May 8, 2007 |
| Some embodiments of the invention provide a method of solving an optimization problem. The problem includes a plurality of elements, and one or more solutions have been previously identified for each element. The method specifies a first solution set that has one identified solution |
| 7197738 |
Method and apparatus for routing |
March 27, 2007 |
| Some embodiments of the invention provide a router that can define a route that has different widths along different directions on the same layer. To facilitate the creation of such a route, some embodiments adaptively define the shape of interconnect-line ends (i.e., the shape of ro |
| 7191112 |
Multiple test bench optimizer |
March 13, 2007 |
| Test benches, simulations, and scripts are invoked in parallel for testing multiple points in a circuit being synthesized in an Analog Mixed Signal environment. A simulation system for simultaneously optimizing performance characteristics in circuit synthesis uses a set of design par |
| 7188327 |
Method and system for logic-level circuit modeling |
March 6, 2007 |
| A method for generating a model for a circuit having logic components is provided. The method includes identifying interface path logic components of the logic components so as to define shell logic, and identifying at least one of the logic components on which a constraint has been |
| 7181708 |
Coverage metric and coverage computation for verification based on design partitions |
February 20, 2007 |
| A method of electronic circuit design includes performing property verification for partitions of a design of an electronic circuit, selecting an outcome for each partition from a plurality of outcome categories, and computing coverage information for each element of the design based |
| 7181705 |
Hierarchical test circuit structure for chips with multiple circuit blocks |
February 20, 2007 |
| A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e.g., an IEEE standard 11 |
| 7181383 |
System and method for simulating a circuit having hierarchical structure |
February 20, 2007 |
| A system for simulating a circuit having hierarchical data structure includes a simulator module having one or more computer programs for 1) creating a static database in accordance with a netlist description of the circuit, where the static database contains topology information of |
| 7177783 |
Shape based noise characterization and analysis of LSI |
February 13, 2007 |
| The invention allows the inclusion of cross-talk coupling and other noise in circuit simulation by considering a resultant glitch in more detail than just its peak value. A set of parameters represents the noise, with an exemplary embodiment using a triangle approximation to a glitch bas |
| 7174529 |
Acute angle avoidance during routing |
February 6, 2007 |
| Determining a route between a start to the target geometry by producing potential route segments and testing the segments to determine whether they create acute angles in the route. If a potential route segment produces an acute angle in the route, it is prevented from being included |
| 7171635 |
Method and apparatus for routing |
January 30, 2007 |
| Some embodiments of the invention provide a method of identifying global routes for nets in a region of a layout with multiple layers, where each net has a set of routable elements. The method partitions each layer of the region into several sub-regions. For each net, the method then |
| 7168053 |
Method and system for implementing an analytical wirelength formulation |
January 23, 2007 |
| Disclosed are methods and systems for specifying an analytical wirelength formulation that is continuous along with its derivative. One approach performs a wirelength estimate in which a continuous formulation is employed to identify and use a bounding box to enclose circuit elements |
| 7168041 |
Method and apparatus for table and HDL based design entry |
January 23, 2007 |
| Views for signals and instances are provided in a table based design entry system. The signal view allows a designer to enter signals to be used in a design. The signals may be individually entered or imported from pre-defined or external packages of signals. The instance view allows the |
| 7168005 |
Programable multi-port memory BIST with compact microcode |
January 23, 2007 |
| A microcode programmable built-in-self-test (BIST) circuit and method for testing a multiported memory via multiple ports, either simultaneously or sequentially, as directed by a microcode instruction word. The microcode instruction word contains a plurality of executable subinstructions |
| 7159217 |
Mechanism for managing parallel execution of processes in a distributed computing environment |
January 2, 2007 |
| According to one aspect, a work request that specifies first and second jobs is received. The first job comprises a first task and the second job comprises a second task. The work request is processed to automatically determine whether the jobs have any dependencies that have not been |
| 7155697 |
Routing method and apparatus |
December 26, 2006 |
| A method for routing of some embodiments defines global routes for nets in an arbitrary region of a circuit layout in which each net has a set of pins. The method uses a first set of lines of measure the length of the global routes, a second set of lines to measure congestion of the glob |
| 7155694 |
Trial placement system with cloning |
December 26, 2006 |
| In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a "master module" and the others designated "c |
| 7155440 |
Hierarchical data processing |
December 26, 2006 |
| Some embodiments of the invention provide a method for processing a hierarchical data structure that includes a parent data set and first and second child data sets of the parent data set. The parent and first and second child data sets includes several data tuples. From the second c |
| 7143383 |
Method for layout of gridless non manhattan integrated circuits with tile based router |
November 28, 2006 |
| The present invention introduces a method for implementing a gridless non Manhattan router by modifying an existing gridless Manhattan router. In the method of the present invention, a tile based router that uses tiles to represent circuit geometry or free space between circuit geometry |
| 7143382 |
Method and apparatus for storing routes |
November 28, 2006 |
| Some embodiments of the invention provide a method of pre-computing routes for nets a region of a design layout. These routes are used by a router that uses a set of partitioning lines to partition the region into a plurality of sub-regions. For each particular set of potential sub-r |
| 7143136 |
Secure inter-company collaboration environment |
November 28, 2006 |
| An environment is described in which multiple companies can securely collaborate on a design or other project. The environment includes a set of resources residing on a set of one or more utility servers maintained by a first company, an access control mechanism for controlling access to |
| 7143021 |
Systems and methods for efficiently simulating analog behavior of designs having hierarchical st |
November 28, 2006 |
| A machine-implemented, simulations-supporting system creates a hierarchy of data structures for simplifying the task of identifying iso-topological, and iso-geometric, and iso-static instances of subcircuit-definitions. The behaviors of such isomorphic and iso-static instances can be |
| 7143020 |
Method and system for generic inference of sequential elements |
November 28, 2006 |
| A method for inferring a requested data input function of a sequential cell from a library of candidate cells, wherein the requested cell and the candidate cell are expressed as polynoms and then divided. The method generates polynomial expressions of the inhibition, transformation and |
| 7139994 |
Method and apparatus for pre-computing routes |
November 21, 2006 |
| Some embodiments provide a method of pre-computing routes for nets in a region of an integrated circuit ("IC") layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. For a particular set |
| 7139987 |
Analog integrated circuit layout design |
November 21, 2006 |
| In an automated integrated circuit design, if the performances of a layout of circuit devices are not within predetermined tolerances of performance specifications, at least one of the circuit devices is resized or repositioned and an updated value of a device parameter for each resized |
| 7137093 |
Post-placement timing optimization of IC layout |
November 14, 2006 |
| When an IC layout is to include time-constrained signal paths, a placement plan defining positions of cells forming the IC is analyzed to estimate lengths of nets needed to interconnect the cells based on the positions of cells included in those signal paths. A capacitance and resistance |
| 7137084 |
Similarity-driven synthesis for equivalence checking of complex designs |
November 14, 2006 |
| A method for modeling a circuit design includes synthesizing the circuit design to create a first gate-level representation of the circuit design. The method also includes analyzing a second gate-level representation of the circuit design to learn architecture information, and resynthesi |
| 7136947 |
System and method for automatically synthesizing interfaces between incompatible protocols |
November 14, 2006 |
| A system and method for enabling Intellectual Property (IP) Blocks to be reused at a system level. The present invention represents the IP blocks as blocks that exchange messages without needing to represent the functionality of the IP blocks. The implementations of these IP blocks e |
| 7127688 |
Method and apparatus for determining interactive electromagnetic effects among conductors of a m |
October 24, 2006 |
| To estimate a distribution of voltages or currents in the layers of a multi-layer circuit, an exemplary current flow in each layer is discretized into a number of current vector elements and at least one scalar charge element related to the charge associated with each current vector |
| 7124383 |
Integrated proof flow system and method |
October 17, 2006 |
| Integrated proof flow methods and apparatuses are discussed. Integrated proof flow refers to attempting both formal verification and nonformal verification. A coverage metric can be changed by both attempting formal verification and by attempting nonformal verification. Some embodiments |
| 7117500 |
Mechanism for managing execution of interdependent aggregated processes |
October 3, 2006 |
| Dependencies can be specified between jobs that are constituent to a unit of work, which are automatically determined or identified by processing a work request that defines the work. For example, a second job can be specified as depending on a first job meeting a particular condition. |
| 7117470 |
Method and system for distributing clock signals on non Manhattan semiconductor integrated circu |
October 3, 2006 |
| The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal |
| 7117468 |
Layouts with routes with different spacings in different directions on the same layer, and metho |
October 3, 2006 |
| Some embodiments of the invention provide a method of routing nets in a multi-layer integrated-circuit ("IC") layout. For each particular net in a set of nets, the method specifies different spacing constraints for routing the particular net in different directions on the same layer. It |
| 7114141 |
Method and apparatus for decomposing a design layout |
September 26, 2006 |
| Some embodiments of the invention provide a method of decomposing a design layout. The method decomposes the layout into a tessellated graph with several edges. It then computes the capacity of the edges based on a interconnect line model that is used to connect elements in the design |
| 7114138 |
Method and apparatus for extracting resistance from an integrated circuit design |
September 26, 2006 |
| The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, complex resistance extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub prob |
| 7107564 |
Method and apparatus for routing a set of nets |
September 12, 2006 |
| One embodiment of the invention is a method of specifying routes for a group of nets. The method identifies different routing solutions for the group of nets. It then selects the best routing solution. |
| 7107556 |
Method and system for implementing an analytical wirelength formulation for unavailability of ro |
September 12, 2006 |
| Disclosed are methods and systems for formulating a wirelength estimate that takes into account whether any of the routing directions are unavailable. Under certain circumstances, one or more of the routing layers may not be available for routing a wire. If this occurs, then the boun |
| 7103816 |
Method and system for reducing test data volume in the testing of logic products |
September 5, 2006 |
| A method and system for reducing test data volume in the testing of logic products such as integrated circuit chips. Test data loaded by a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises "care" bits and " |
| 7103524 |
Method and apparatus for creating an extraction model using Bayesian inference implemented with |
September 5, 2006 |
| A system for using machine learning based upon Bayesian inference using a hybrid Monte Carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The m |
| 7100143 |
Method and apparatus for pre-tabulating sub-networks |
August 29, 2006 |
| Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated paramet |
| 7100137 |
Method and apparatus for quantifying the quality of placement configurations in a partitioned re |
August 29, 2006 |
| One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then |
| 7100129 |
Hierarchical gcell method and mechanism |
August 29, 2006 |
| A method of analyzing a design of an electronic circuit includes tessellating the design into a grid of rectangles, selecting at least one rectangle as a first level parent rectangle, and generating a plurality of second level child rectangles based on the first level parent rectangl |
| 7100128 |
Zone tree method and mechanism |
August 29, 2006 |
| A method of analyzing a design of an electronic circuit uses slices. The method includes generating one or more slices, each slice comprising a contiguous region of the design, and generating an set comprising one or more bins for each slice. A search for an object may be performed by |
| 7100124 |
Interface configurable for use with target/initiator signals |
August 29, 2006 |
| Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of designing an integrated circuit includes several steps. In one step, a foundation block for |
| 7096449 |
Layouts with routes with different widths in different directions on the same layer, and method |
August 22, 2006 |
| Some embodiments of the invention provide a method of routing nets in a multi-layer integrated-circuit ("IC") layout. For a particular net, the method specifies widths for routing the particular net in different directions on the same layer. It then defines a particular route for the |
| 7096448 |
Method and apparatus for diagonal routing by using several sets of lines |
August 22, 2006 |
| Some embodiments provide a method of routing nets within a region of an integrated-circuit ("IC") layout. The method uses a first set of lines to partition the IC region into a plurality of sub-regions. In addition, the method uses a second set of lines to measure congestion of routes fo |
| 7096445 |
Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated ci |
August 22, 2006 |
| Disclosed is an improved approach for maintaining the structures for objects in a layout. A single type of structure is maintained that can be used to store or track a polygon of any shape, as long as the shape possesses a supported number of sides. The structure is capable of suppor |
| 7095748 |
Bridging apparatus for interconnecting a wireless PAN and a wireless LAN |
August 22, 2006 |
| A Wireless bridge conjoins two previously incompatible technologies within a single device to leverage the strengths of each. The Wireless bridge marries the Personal Area Network (PAN) technology of Bluetooth as described in Bluetooth Specification Version 1.0B with the Wireless Local |
| 7093259 |
Hierarchically structured logging for computer work processing |
August 15, 2006 |
| A work request is processed and interpreted to automatically establish job data structures associated with jobs constituent to the work and data storage structures associated with tasks constituent to the work. Further, parent-child relationships between jobs, sub-jobs and tasks are |
| 7093221 |
Method and apparatus for identifying a group of routes for a set of nets |
August 15, 2006 |
| Some embodiments of the invention provide a method of identifying a group of routes for a set of nets. The group of routes includes one route for each net in the set of nets. The method identifies a set of routes for each net. It then iteratively selects one identified route for each net |
| 7093220 |
Method for generating constrained component placement for integrated circuits and packages |
August 15, 2006 |
| A method for determining component placement in a circuit includes forming a tree structure that defines the placement of each of a plurality of components associated with the tree structure on a first side, a second side or on both sides of a symmetry line, with at least one component |
