| Patent Number |
Title Of Patent |
Date Issued |
| 7434183 |
Method and system for validating a hierarchical simulation database |
October 7, 2008 |
| System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing representations of the circuit on a display, a memory for storing information of the circuit, |
| 7428712 |
Design optimization using approximate reachability analysis |
September 23, 2008 |
| Aspects of computing design invariants, by using approximate reachability analysis, include reducing the circuit model for verification and synthesis. Further included is computing invariants using approximate reachability analysis to optimize a circuit model by identifying a plurali |
| 7428477 |
Simulation of electrical circuits |
September 23, 2008 |
| A method, computer program product, and apparatus for simulating circuits. The method comprises modeling a circuit with an appropriate system of equations, partitioning a time interval on which the system of equations is defined, producing an interpolating polynomial on the time interval |
| 7424703 |
Method and system for simulation of mixed-language circuit designs |
September 9, 2008 |
| A method for simulation of mixed-language circuit designs is disclosed. In one embodiment, an object-oriented language module is natively instantiated within a hardware description language based design. In another embodiment, a hardware description language module is natively instan |
| 7418693 |
System and method for analysis and transformation of layouts using situations |
August 26, 2008 |
| Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the |
| 7418684 |
Systems, methods, and apparatus to perform static timing analysis and optimization for multi-mod |
August 26, 2008 |
| A method and an apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks have been disclosed. In one embodiment, the method includes determining a plurality of sensitization conditions associated with one or more clock signals in a circuit ne |
| 7418683 |
Constraint assistant for circuit design |
August 26, 2008 |
| A computer aided design tool and method for designing IC layouts by recommending subcircuit layout constraints based upon an automated identification from a circuit schematic of subcircuit types requiring special IC layout constraints. Subcircuit types are identified on the basis of |
| 7415403 |
Systems and methods for efficiently simulating analog behavior of designs having hierarchical st |
August 19, 2008 |
| A method for simulating analog behavior of a circuit in a simulation system includes representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set o |
| 7412682 |
Local preferred direction routing |
August 12, 2008 |
| Some embodiments of the invention provide a method for routing. The method defines at least one wiring layer that has at least two regions with different local preferred wiring directions. The method then uses the differing local preferred wiring directions to define a global route on |
| 7412681 |
DC path checking in a hierarchical circuit design |
August 12, 2008 |
| A computer implemented method is provided for use in evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing a circuit path within a higher level circuit that includes a reference potential connection, to identify a po |
| 7409656 |
Method and system for parallelizing computing operations |
August 5, 2008 |
| Disclosed is an improved method and system for implementing parallel processing of computing operations by effectively handling dependencies between different sequences of computing operations. In some approaches, some or all operations corresponding to dependencies between different |
| 7409328 |
System and method for communicating simulation solutions between circuit components in a hierarc |
August 5, 2008 |
| A system for communicating simulation solutions between circuit components in a hierarchical data structure includes a simulator module having one or more computer programs for representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a p |
| 7406405 |
Method and system for design verification using proof-based abstraction |
July 29, 2008 |
| A design verifier includes a bounded model checker, an abstractor and an unbounded model checker. The bounded model checker verifies a property to a depth K and either finds a counterexample, or generates a proof in the form of a directed acyclic graph. If no counterexample is found, the |
| 7398503 |
Method and apparatus for pre-tabulating sub-networks |
July 8, 2008 |
| A method for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network based on the parameter. In some embodiments, the generated sub-network has several circuit elements, pe |
| 7398498 |
Method and apparatus for storing routes for groups of related net configurations |
July 8, 2008 |
| Some embodiments of the invention provide a method that pre-computes routes for groups of related net configurations. These routes are used by a router that uses a set of partitioning lines to partition a region of a design layout into a plurality of sub-regions. The method identifies |
| 7397320 |
Non-uniform transmission line for reducing cross-talk from an aggressor transmission line |
July 8, 2008 |
| A non-uniform transmission line, including at least a first section with length L1, uniform width W1 and thickness h1, and a second section with length L2, uniform width W2 and thickness h2, joined together to form a composite structure and arranged in any of at least three distinct |
| 7395516 |
Manufacturing aware design and design aware manufacturing |
July 1, 2008 |
| Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit ("IC"). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then |
| 7393755 |
Dummy fill for integrated circuits |
July 1, 2008 |
| A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ |
| 7392255 |
Federated system and methods and mechanisms of implementing and using such a system |
June 24, 2008 |
| A federated system and methods and mechanisms of implementing and using such a system is disclosed. In some embodiments, one or more mappings are created between a taxonomy view at a node and one or more taxonomies of one or more data sources. The one or more data sources can then be |
| 7392170 |
System and method for dynamically compressing circuit components during simulation |
June 24, 2008 |
| A system for dynamically compressing circuit components during simulating of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) selecting a group of leaf circuits from the first and second branches for simulation, 2) if |
| 7386813 |
Transformation of simple subset of PSL into SERE implication formulas for verification with mode |
June 10, 2008 |
| The disclosure presents a formulation to support simulatable subset (also known as `simple-subset`) of a property specification language. This method is applicable for model checking and simulation. In this formulation, the `simple-subset` is transformed to a set of basic formulas. V |
| 7383524 |
Structure for storing a plurality of sub-networks |
June 3, 2008 |
| Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated paramet |
| 7383521 |
Characterization and reduction of variation for integrated circuits |
June 3, 2008 |
| A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circu |
| 7380226 |
Systems, methods, and apparatus to perform logic synthesis preserving high-level specification |
May 27, 2008 |
| A method and an apparatus to perform logic synthesis preserving high-level specification and to check that a common specification (CS) of two circuits is correct have been disclosed. In one embodiment, the method includes building a circuit N.sub.2 that preserves a predefined specifi |
| 7380220 |
Dummy fill for integrated circuits |
May 27, 2008 |
| A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ |
| 7373620 |
Methods and mechanisms for extracting and reducing capacitor elements |
May 13, 2008 |
| A method of extracting capacitance from a layout record includes imposing voltages on conductors in a layout record, and determining a total charge for each of the conductors to obtain a capacitor element for the conductors. A method of extracting capacitance from a layout record inc |
| 7373618 |
Method and system for selection and replacement of subcircuits in equivalence checking |
May 13, 2008 |
| A system, method, computer program, and article of manufacture for generating a golden circuit including datapath components for equivalence checking of synthesized revised circuit. The method includes generating a set of static, dynamic and derived candidates for the datapath component |
| 7373289 |
Electrical isomorphism |
May 13, 2008 |
| Method and system for determining electrical isomorphism between two electrical networks are disclosed. In one embodiment, the method includes representing the circuit as a hierarchically-arranged set of branches. The hierarchically-arranged set of branches including a first branch that |
| 7367008 |
Adjustment of masks for integrated circuit fabrication |
April 29, 2008 |
| A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithogr |
| 7367006 |
Hierarchical, rules-based, general property visualization and editing method and system |
April 29, 2008 |
| A hierarchical, rule-based, general property visualization and editing system, method, and computer program for circuit designs is provided. A general rules dictionary is created or obtained that determines how the rules will be applied to the circuit design hierarchy. A hierarchical |
| 7363605 |
Eliminating false positives in crosstalk noise analysis |
April 22, 2008 |
| A method for analyzing a circuit design identifies a possible noise fault for a timing interval based on a timing analysis of a victim net and at least one aggressor net of the circuit design and determines whether the noise fault is feasible based on a behavioral representation of the |
| 7363598 |
Dummy fill for integrated circuits |
April 22, 2008 |
| A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ |
| 7363099 |
Integrated circuit metrology |
April 22, 2008 |
| Sites to be measured on a device that is to be fabricated using at least one fabrication process, are selected based on a pattern-dependent model of the process. A metrology tool to measure a parameter of a semiconductor device includes a control element to select sites for measureme |
| 7360179 |
Use of models in integrated circuit fabrication |
April 15, 2008 |
| A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ |
| 7359846 |
Modeling an ASIC based on static pipeline delays |
April 15, 2008 |
| A simulator for a design of an electronic system includes high-level delay models for architecture resources such as ASICs, CPUs, and busses, for example. The delay models of pipelined ASICs compute static pipeline delays which are then implemented by the system simulator. The ASIC delay |
| 7359843 |
Robust calculation of crosstalk delay change in integrated circuit design |
April 15, 2008 |
| A method of delay change determination in an integrated circuit design including a stage with a victim net and one or more aggressor nets capacitively coupled thereto, the method comprising: determining a nominal (noiseless) victim net signal transition; determining a noisy victim ne |
| 7356784 |
Integrated synthesis placement and routing for integrated circuits |
April 8, 2008 |
| A method determining an IC (integrated circuit) design includes: determining one or more design variables, wherein the one or more design variables include one or more device variables and one or more weights; determining one or more net lengths and one or more layout metrics from th |
| 7356783 |
Dummy fill for integrated circuits |
April 8, 2008 |
| A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ |
| 7356519 |
Method and system for solving satisfiability problems |
April 8, 2008 |
| A method and system for solving satisfiability problems is disclosed. In one embodiment, clauses in a satisfiability problem are organized as a chronologically ordered stack. In another embodiment, the activity of each variable in the satisfiability problem is monitored. An activity |
| 7356451 |
Assertion handling for timing model extraction |
April 8, 2008 |
| Disclosed is a method and system for handling timing constraints or assertions for timing model extraction. One disclosed approach for assertion handling is by automatically preserving the integrity of original assertions by retaining existing pins or creating new internal pins. The |
| 7353475 |
Electronic design for integrated circuits based on process related variations |
April 1, 2008 |
| A pattern-dependent model is used to predict variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variations to the integrated circuit and (b) |
| 7353467 |
Method and system for facilitating electronic circuit and chip design using remotely located res |
April 1, 2008 |
| A multi-faceted portal site acts as a server in the context of an n-tier client/server network, and connects electronic designers and design teams to design and verification tool and service providers on the other through a single portal site. Tools and services accessible to users t |
| 7350167 |
Extraction and reduction of capacitor elements using matrix operations |
March 25, 2008 |
| A method for extracting capacitance from a layout record includes solving a matrix equation to obtain a set of capacitors that account for metal fill while eliminating floaters. A method for extracting capacitance from a layout record includes partitioning floaters into disjoint sets, an |
| 7349493 |
Demodulation with separate branches for phase and amplitude |
March 25, 2008 |
| A receiver architecture is disclosed for use in Time-Division Multiple Access (TDMA) and related digital radio applications which combines the principal benefits of the conventional hard-limiting and linear receiver architectures to support switched-antenna diversity and multipath eq |
| 7348824 |
Auto-zero circuit |
March 25, 2008 |
| An auto-zero circuit is disclosed. The auto-zero circuit includes a first set of circuits for implementing a first auto-zero phase and a second set of circuits for implementing a second auto-zero phase. The first set of circuits includes a first differential amplifier and a first feedbac |
| 7346872 |
Functional timing analysis for characterization of virtual component blocks |
March 18, 2008 |
| A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for |
| 7346868 |
Method and system for evaluating design costs of an integrated circuit |
March 18, 2008 |
| Method and system for evaluating design costs of an integrated circuit are disclosed. The method includes choosing a design point for evaluation, dividing circuit specifications of the design point into at least two groups comprising a first group of specifications and a second group of |
| 7340711 |
Method and apparatus for local preferred direction routing |
March 4, 2008 |
| Some embodiments of the invention provide a method for defining routes in a design layout. The method defines at least one particular wiring layer that has at least two regions with different local preferred wiring directions. The method then uses the differing local preferred wiring |
| 7340702 |
Method and apparatus for induction proof |
March 4, 2008 |
| Inductive proof can be an improvement to bounded verification. Forward and backward inductive proof methods are disclosed, which can improve the process of verifying properties of circuit designs. An inductive set of one or more states includes passing a first property of a circuit desig |
| 7337421 |
Method and system for managing design corrections for optical and process effects based on featu |
February 26, 2008 |
| A method for modifying instances of a repeating pattern in an integrated circuit design to correct for perturbations during rendering is described. In the typical embodiment, these corrections are optical proximity corrections that correct for optical effects during the projection of |
