| Patent Number |
Title Of Patent |
Date Issued |
| 7279953 |
Current switch and method of driving the same |
October 9, 2007 |
| A method and apparatus for driving a current switch with a differential drive signal monitors both the temperature of the switch and the current through the switch. The method and apparatus dynamically control the amplitude of the drive signal as a function of the switch temperature and |
| 7277474 |
Finger allocation for a path searcher in a multipath receiver |
October 2, 2007 |
| A technique for allocating fingers in a path searcher of a multipath receiver involves determining a required number of fingers for each multipath region, determining a number of allocated fingers for each multipath region according to an area-based weighting scheme such that each mu |
| 7274321 |
Analog to digital converter |
September 25, 2007 |
| A analog to digital converter, comprising: an input for receiving an input signal to be digitized; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first resi |
| 7272705 |
Early exception detection |
September 18, 2007 |
| A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may b |
| 7272526 |
Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within |
September 18, 2007 |
| An apparatus for measuring the time delay between adjacent clock edges includes target and delay signal paths, a variable delay module in said delay signal path, the delay cell having a delay bias input, and a phase detector having respective inputs coupled to the target and delay signal |
| 7271750 |
Pipelined converter systems with enhanced accuracy |
September 18, 2007 |
| Converter system embodiments are formed with signal-processing stages which include successive signal converters and a preceding signal sampler wherein all but a last one of the stages provides an output signal to a succeeding one of the stages and all of said signal converters generate |
| 7269615 |
Reconfigurable input Galois field linear transformer system |
September 11, 2007 |
| A reconfigurable input Galois field linear transformer system includes a Galois field linear transformer including a matrix of cells; a plurality of storage planes for storing control patterns representing a number of different functions; a storage plane selector circuit for selecting a |
| 7269187 |
Packet detection system and method |
September 11, 2007 |
| A packet detection technique is disclosed in which an average correlation signal is generated representative of the match between a repetitive sequence of symbols; an average power signal is generated representative of the average power in the sequence of symbols; a scaled magnitude of |
| 7268720 |
Converter networks for generation of MDAC reference signals |
September 11, 2007 |
| Reference network embodiments are disclosed that provide reference signals to, for example, switched-capacitor multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters (ADCs). These embodiments are configured to maintain accuracy of the levels of the |
| 7268714 |
Rapid response current measurement system and method |
September 11, 2007 |
| A rapid response measurement is accomplished by providing to a programmable gain amplifier an input to be measured, providing to an analog to digital converter having a predetermined output rate, the output from the programmable gain amplifier, determining when the output is greater |
| 7266676 |
Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays |
September 4, 2007 |
| Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the tag array provides an index to a corresponding entry in the data array, storing in a sele |
| 7266160 |
Method for joint DC offset correction and channel coefficient estimation in a receiver |
September 4, 2007 |
| Although DC offset reduction schemes can be applied in the analog domain, the residual static DCO in baseband is still present, significantly influencing the performance of high-level modulation schemes employed by recent high-data-rate wireless communications standards. In order to |
| 7266077 |
Serial digital communication system and method |
September 4, 2007 |
| A serial digital communication system includes a master device and a plurality of slave devices connected serially between the master device's output and input--thereby forming a closed chain. Each slave device transmits a predetermined number of PWM pulses to the device following it |
| 7265628 |
Margin tracking cascode current mirror system and method |
September 4, 2007 |
| A margin tracking cascode current mirror system including a current mirror circuit having a current source device having a predetermined operating voltage for providing a current to a load, a cascode circuit interconnected between the current mirror and the load for controlling the o |
| 7265625 |
Amplifier systems with low-noise, constant-transconductance bias generators |
September 4, 2007 |
| Amplifier systems are provided with bias generators that substantially stabilize operating points of system parameters (e.g., drain current and transconductance) over PVT variations, substantially reduce body effects and Early effects, and substantially reduce system output noise. These |
| 7265615 |
Multiple differential amplifier system and method for transconductance mismatch compensation |
September 4, 2007 |
| A multiple differential amplifier system and method for transconductance mismatch compensation which in a first phase connects to a differential switched input of a null amplifier, the differential signal input of the main amplifier, inverted, for compensating for offset errors and t |
| 7265594 |
Methods and apparatus for generating timing signals |
September 4, 2007 |
| One embodiment of the invention is directed to a method, comprising acts of generating a plurality of delay signals, and processing at least first and second delay signals of the plurality of delay signals to generate a first timing signal. Another embodiment of the invention is directed |
| 7263152 |
Phase-locked loop structures with enhanced signal stability |
August 28, 2007 |
| Phase-locked loop structures are provided that facilitate enhanced stability of loop-generated signals. They include an oscillator network, a feedback loop and a controller. The oscillator network generates a loop output signal with a frequency that varies in response to a control vo |
| 7262726 |
Quadrature bandpass .DELTA..SIGMA. converter |
August 28, 2007 |
| An improved quadrature bandpass .DELTA..SIGMA. converter includes a loop filter, an ADC responsive to the loop filter, and a first feedback DAC responsive to the ADC; a first summing circuit is responsive to the first DAC and an analog input for providing an input to the loop filter; a |
| 7260367 |
Edge power detector/controller |
August 21, 2007 |
| Described is a closed-loop power detector/controller for wireless systems employing a non-constant amplitude envelope modulation scheme. Any AM component in the feedback signal resulting from non-constant amplitude envelope signals is eliminated via feed-forward cancellation of the e |
| 7259706 |
Balanced dual resistor string digital to analog converter system and method |
August 21, 2007 |
| A digital to analog converter system is disclosed for receiving an input signal and a sign bit signal that is indicative of the sign of the input signal. The digital to analog converter system includes first and second pairs of resistor strings, and first and second switching networks. A |
| 7253686 |
Differential amplifiers with enhanced gain and dynamic range |
August 7, 2007 |
| Differential amplifier embodiments are provided for amplifying input signals with enhanced gain and dynamic range. They include first and second amplifier stages and at least one common-mode feedback circuit that is arranged to mirror and adjust a tail current to control the common-m |
| 7253678 |
Accurate cascode bias networks |
August 7, 2007 |
| Bias networks are provided for accurate generation of biases of cascode transistor arrangements. Network embodiments generate a voltage that accurately biases the transistor of a cascode arrangement at a selected point in its saturation region and this voltage is accurately transferred |
| 7253597 |
Curvature corrected bandgap reference circuit and method |
August 7, 2007 |
| A curvature corrected bandgap reference circuit comprises a first bipolar transistor having a base-emitter voltage V.sub.be1 and operated such that it has a constant operating current, and a second bipolar transistor having a base-emitter voltage V.sub.be2 and operated such that it has a |
| 7251299 |
Time delay estimator |
July 31, 2007 |
| A system for time delay estimation in a discrete time processing system includes a cross correlator that performs cross correlation on a first signal and a second signal, and provides a cross correlated output signals indicative thereof. A lag smoother receives the cross correlated o |
| 7250885 |
System and method for using timing skew estimation with a non-sequential time-interleaved analog |
July 31, 2007 |
| A multi-channel analog-to-digital converter system includes an array of sub-analog-to-digital converters wherein within the array of sub-analog-to-digital converters, there is at least one designated reference analog-to-digital converter. The analog-to-digital converter system also i |
| 7250880 |
Analog to digital converter |
July 31, 2007 |
| An analog to digital converter comprising at least two analog to digital conversion engines and a controller for controlling the operation of the analog to digital conversion engines such that during a first phase of an analog to digital conversion process the engines collaborate such th |
| 7250819 |
Input tracking current mirror for a differential amplifier system |
July 31, 2007 |
| An input tracking current mirror for a differential amplifier system includes a current mirror having an input leg and an output leg, a differential amplifier including a first set of at least two transconductance components, each having at least one input terminal for receiving inpu |
| 7248661 |
Data transfer between phase independent clock domains |
July 24, 2007 |
| An integrated circuit arrangement clocked by a single clock having variable delays to different regions of said arrangement such that said regions are partially synchronized to each other, the arrangement comprising: a data transfer buffer for buffering a data stream for transfer bet |
| 7248646 |
Digital reconfigurable core for multi-mode base-band transmitter |
July 24, 2007 |
| A reconfigurable communication transmitter core includes a digital pulse-shaping filter to perform pulse-shaping operations upon a digital modulated signal and a finite state machine to controls operation and reconfiguration of the digital pulse-shaping filter. A first memory stores |
| 7248450 |
Pad cell with multiple signal paths |
July 24, 2007 |
| An integrated circuit is described including internal circuitry and having at least one external connection. A pad cell is electrically interposed between the external connection and the internal circuitry, the pad cell comprising a first group of components adapted to protect the intern |
| 7248192 |
Digital to analog converter and a ground offset compensation circuit |
July 24, 2007 |
| A digital to analog converter comprising: a digital to analog conversion core adapted to receive at least one reference voltage and a digital word to be converted, and to output an analog voltage as a function of the digital word and the at least one reference voltage; a sensing circuit |
| 7248035 |
Automatic test equipment pin channel with T-coil compensation |
July 24, 2007 |
| A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably com |
| 7245244 |
Correction methods and structures for analog-to-digital converter transfer functions |
July 17, 2007 |
| Methods and structures are provided to improve the transfer functions of analog-to-digital converter systems. They address the converter error function that corresponds to a converter's transfer function. In particular, they provide a corrector with a corrector transfer function that |
| 7242428 |
Image sensor using multiple array readout lines |
July 10, 2007 |
| In one embodiment, an image sensor includes an area pixel array, column readout lines, and array readout lines, wherein the area pixel array includes columns of pixels, each including pixels of a first type, each column readout line is selectively coupled to outputs of the pixels of |
| 7242230 |
Microprocessor with power saving clock |
July 10, 2007 |
| A data processing chip with a flexible timing system and method for supplying clocks to a digital data processing system useful for power conservation. A phase locked loop generates a master clock from which a core clock and a system clock are derived. The frequency of each of the co |
| 7240170 |
High/low priority memory |
July 3, 2007 |
| Methods and apparatus are provided for achieving low latency for high priority tasks in digital processing systems. A digital signal processor includes a core processor and a level one memory. In some embodiments, a store buffer is configured to hold write information for the level one |
| 7240129 |
DMA controller having programmable channel priority |
July 3, 2007 |
| A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; fir |
| 7236897 |
Group metering system for power meters |
June 26, 2007 |
| A group metering method (and system) for monitoring electrical energy consumption by a plurality of proximate users replaces multiple individual user-meters by a single electronic meter. A single computational engine computes consumed energy values by the users and deploys a single s |
| 7236541 |
Translation loop modulator |
June 26, 2007 |
| A translation loop modulator for a transmission circuit in a communication system includes an input modulation unit for receiving at least one input signal that is representative of information to be modulated. The input modulation unit also receives a feedback signal, produces an interm |
| 7236111 |
Linearizing methods and structures for amplifiers |
June 26, 2007 |
| Methods and structures are provided to enhance the linearity of amplifiers such as those which include a complementary common-collector amplifier stage. The methods and structures configure this stage so that each transistor of the stage drives an output port through a linearizing re |
| 7236110 |
Sample rate converter for reducing the sampling frequency of a signal by a fractional number |
June 26, 2007 |
| A sample rate converter reduces the sampling rate of a signal by a fractional number U/D, where U represents an up-sampling rate and D represents a down-sampling rate. The converter comprises an input for receiving an input data stream at a first rate and an FIR filtering stage. The |
| 7236011 |
High-speed differential logic buffer |
June 26, 2007 |
| A circuit for a high speed digital buffer has an active load circuit connected to an output of the digital buffer. The active load circuit loads the buffer output with an active inductance to reduce the RC time constant at the buffer output. The active load circuit may be based on tw |
| 7235983 |
One terminal capacitor interface circuit |
June 26, 2007 |
| A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for cha |
| 7233179 |
Output stage interface circuit for outputting digital data onto a data bus |
June 19, 2007 |
| An output stage interface circuit (1) comprises a main bipolar transistor (Q1) coupling a data output terminal (5) to a first rail (2) to which the positive of the power supply voltage (V.sub.DD) is applied, and a substrate diffusion isolated main NMOS transistor (MN1) coupling the data |
| 7233120 |
Optimal fan presence detection |
June 19, 2007 |
| Detecting the presence of an electric fan is described. A current sink circuit is coupled to a pulse width drive output of a fan control circuit. A logic state in a logic input buffer is defined based on current flow through the current sink. The logic state indicates if a fan is cou |
| 7232705 |
Integrated circuit bond pad structures and methods of making |
June 19, 2007 |
| A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second |
| 7230410 |
Accurate high-speed current sources |
June 12, 2007 |
| Current source embodiments are provided which generate an output current pulse whose initial and terminal slew rates are enhanced with initial and terminal generators that respectively provide an initial current pulse at initiation of the command signal and a terminal current pulse at |
| 7228373 |
Serial digital communication system and method |
June 5, 2007 |
| A communication system includes a master device which communicates with a chain of serially-connected slave devices. The master originates messages, each of which is intended for a particular `target` slave device. Each message contains a `distance to target device` value equal to th |
| 7227481 |
Feedback DAC chopper stabilization in a CT single-ended multi-bit sigma delta ADC |
June 5, 2007 |
| A multi-bit sigma-delta analog-to-digital converter (ADC) has a single-ended input for receiving an analog input signal. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a multibit digital feedback signal from a Fla |
