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Analog Devices, Inc. Patents
Analog Devices, Inc.
Norwood, MA
No. of patents:

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Patent Number Title Of Patent Date Issued
7295042 Buffer November 13, 2007
A switched capacitor buffer operating by the push-pull method is taught. The buffer may include a pull-up device and a pull-down device. A switched capacitor circuit may be used to control the pull-up device and the pull-down device to achieve accurate push-pull operation. According
7293121 DMA controller utilizing flexible DMA descriptors November 6, 2007
A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; fir
7292649 3G radio November 6, 2007
A homodyne receiver is provided for receiving GSM and UMTS transmissions. The receiver may also be used for other transmission schemes. The receiver includes an electronically reconfigurable low pass filter and an off set generator for providing DC offset correction for offsets which
7292100 Interpolated variable gain amplifier with multiple active feedback cells November 6, 2007
An interpolated variable gain amplifier (VGA) utilizes multiple active feedback cells. The active feedback cells may be implemented as transconductance (gm) cells that replicate gm cells in the interpolated input stages.
7292044 Integrating time measurement circuit for a channel of a test card November 6, 2007
In a first embodiment of the invention there is provided an electronic chip for use with an automatic testing equipment device testing a device under test. The device under test has a plurality of pins and the electronic chip is placed in a channel of a test card that is associated w
7289698 High bitrate transport over multimode fibers October 30, 2007
A multimode fiber system includes a transmitter for transmitting an optical signal and a receiver that receives the optical signal. At least one mode filter is coupled between the receiver and the transmitter and passes only a specific set of fiber modes from the transmitter to be re
7288993 Small signal amplifier with large signal output boost stage October 30, 2007
A small signal amplifier with a large signal output boost stage are connected between first and second supply rails. The small signal amplifier receives first and second input signals and provides an output signal at an output node which drives a load. Under small signal conditions,
7288940 Galvanically isolated signal conditioning system October 30, 2007
A galvanically isolated signal conditioning system includes a signal conditioning circuit on an integrated circuit chip; a flying capacitor; and a galvanically isolating MEMS switching device on an integrated circuit chip for selectively switching the flying capacitor from across a p
7287428 Inertial sensor with a linear array of sensor elements October 30, 2007
An inertial sensor includes at least one pair of sensor elements arranged in a linear array. Each sensor element has a frame and a movable mass suspended within the frame. The frames of each pair of sensor elements may be coupled so that the frames are allowed to move in anti-phase to
7286075 Analog to digital converter with dither October 23, 2007
An analog to digital converter is provided comprising an array of capacitors for sampling an input, each capacitor having at least one associated switch for controllably connecting a terminal of the capacitor to a first reference voltage or to a second reference voltage; and a sequen
7285994 Rotational frequency detector system October 23, 2007
A rotational frequency detector system including a rotational frequency detector responsive to a data signal and a clock signal. The rotational frequency detector is configured to compare the frequency of the clock signal to the frequency of the data signal to define frequency up and
7283628 Programmable data encryption engine October 16, 2007
A programmable data encryption engine for performing the cipher function of the data encryption standard (DES) algorithm includes a Galois field linear transformer system (GFLT) responsive to a first input data block to execute an E permutation to obtain an expanded data block and combin
7283079 Digital to analog converter having a single cyclic resistor string and multiple current sources October 16, 2007
A current driven DAC architecture uses a single resistance string arranged to have a cyclic configuration and a plurality of nodes, one of the nodes being connected to a known potential, e.g., ground potential, and at least two current sources connected to selected ones of said nodes
7279986 Buffer amplifiers with enhanced efficiency October 9, 2007
Buffer amplifiers are provided that demonstrate enhanced efficiency because they include current sources which are configured to be switched off during operational modes in which the amplifiers' output signals are not needed. Amplifier embodiments include charge-transfer transistors and
7279968 Amplifier output voltage swing extender circuit and method October 9, 2007
An amplifier output voltage swing extender circuit comprises a differential amplifier powered between first and second power supply rails, which receives first and second input signals at non-inverting and inverting inputs, respectively, and provides an output at a first output node.
7279953 Current switch and method of driving the same October 9, 2007
A method and apparatus for driving a current switch with a differential drive signal monitors both the temperature of the switch and the current through the switch. The method and apparatus dynamically control the amplitude of the drive signal as a function of the switch temperature and
7277474 Finger allocation for a path searcher in a multipath receiver October 2, 2007
A technique for allocating fingers in a path searcher of a multipath receiver involves determining a required number of fingers for each multipath region, determining a number of allocated fingers for each multipath region according to an area-based weighting scheme such that each mu
7274321 Analog to digital converter September 25, 2007
A analog to digital converter, comprising: an input for receiving an input signal to be digitized; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first resi
7272705 Early exception detection September 18, 2007
A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may b
7272526 Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within September 18, 2007
An apparatus for measuring the time delay between adjacent clock edges includes target and delay signal paths, a variable delay module in said delay signal path, the delay cell having a delay bias input, and a phase detector having respective inputs coupled to the target and delay signal
7271750 Pipelined converter systems with enhanced accuracy September 18, 2007
Converter system embodiments are formed with signal-processing stages which include successive signal converters and a preceding signal sampler wherein all but a last one of the stages provides an output signal to a succeeding one of the stages and all of said signal converters generate
7269615 Reconfigurable input Galois field linear transformer system September 11, 2007
A reconfigurable input Galois field linear transformer system includes a Galois field linear transformer including a matrix of cells; a plurality of storage planes for storing control patterns representing a number of different functions; a storage plane selector circuit for selecting a
7269187 Packet detection system and method September 11, 2007
A packet detection technique is disclosed in which an average correlation signal is generated representative of the match between a repetitive sequence of symbols; an average power signal is generated representative of the average power in the sequence of symbols; a scaled magnitude of
7268720 Converter networks for generation of MDAC reference signals September 11, 2007
Reference network embodiments are disclosed that provide reference signals to, for example, switched-capacitor multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters (ADCs). These embodiments are configured to maintain accuracy of the levels of the
7268714 Rapid response current measurement system and method September 11, 2007
A rapid response measurement is accomplished by providing to a programmable gain amplifier an input to be measured, providing to an analog to digital converter having a predetermined output rate, the output from the programmable gain amplifier, determining when the output is greater
7266676 Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays September 4, 2007
Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the tag array provides an index to a corresponding entry in the data array, storing in a sele
7266160 Method for joint DC offset correction and channel coefficient estimation in a receiver September 4, 2007
Although DC offset reduction schemes can be applied in the analog domain, the residual static DCO in baseband is still present, significantly influencing the performance of high-level modulation schemes employed by recent high-data-rate wireless communications standards. In order to
7266077 Serial digital communication system and method September 4, 2007
A serial digital communication system includes a master device and a plurality of slave devices connected serially between the master device's output and input--thereby forming a closed chain. Each slave device transmits a predetermined number of PWM pulses to the device following it
7265628 Margin tracking cascode current mirror system and method September 4, 2007
A margin tracking cascode current mirror system including a current mirror circuit having a current source device having a predetermined operating voltage for providing a current to a load, a cascode circuit interconnected between the current mirror and the load for controlling the o
7265625 Amplifier systems with low-noise, constant-transconductance bias generators September 4, 2007
Amplifier systems are provided with bias generators that substantially stabilize operating points of system parameters (e.g., drain current and transconductance) over PVT variations, substantially reduce body effects and Early effects, and substantially reduce system output noise. These
7265615 Multiple differential amplifier system and method for transconductance mismatch compensation September 4, 2007
A multiple differential amplifier system and method for transconductance mismatch compensation which in a first phase connects to a differential switched input of a null amplifier, the differential signal input of the main amplifier, inverted, for compensating for offset errors and t
7265594 Methods and apparatus for generating timing signals September 4, 2007
One embodiment of the invention is directed to a method, comprising acts of generating a plurality of delay signals, and processing at least first and second delay signals of the plurality of delay signals to generate a first timing signal. Another embodiment of the invention is directed
7263152 Phase-locked loop structures with enhanced signal stability August 28, 2007
Phase-locked loop structures are provided that facilitate enhanced stability of loop-generated signals. They include an oscillator network, a feedback loop and a controller. The oscillator network generates a loop output signal with a frequency that varies in response to a control vo
7262726 Quadrature bandpass .DELTA..SIGMA. converter August 28, 2007
An improved quadrature bandpass .DELTA..SIGMA. converter includes a loop filter, an ADC responsive to the loop filter, and a first feedback DAC responsive to the ADC; a first summing circuit is responsive to the first DAC and an analog input for providing an input to the loop filter; a
7260367 Edge power detector/controller August 21, 2007
Described is a closed-loop power detector/controller for wireless systems employing a non-constant amplitude envelope modulation scheme. Any AM component in the feedback signal resulting from non-constant amplitude envelope signals is eliminated via feed-forward cancellation of the e
7259706 Balanced dual resistor string digital to analog converter system and method August 21, 2007
A digital to analog converter system is disclosed for receiving an input signal and a sign bit signal that is indicative of the sign of the input signal. The digital to analog converter system includes first and second pairs of resistor strings, and first and second switching networks. A
7253686 Differential amplifiers with enhanced gain and dynamic range August 7, 2007
Differential amplifier embodiments are provided for amplifying input signals with enhanced gain and dynamic range. They include first and second amplifier stages and at least one common-mode feedback circuit that is arranged to mirror and adjust a tail current to control the common-m
7253678 Accurate cascode bias networks August 7, 2007
Bias networks are provided for accurate generation of biases of cascode transistor arrangements. Network embodiments generate a voltage that accurately biases the transistor of a cascode arrangement at a selected point in its saturation region and this voltage is accurately transferred
7253597 Curvature corrected bandgap reference circuit and method August 7, 2007
A curvature corrected bandgap reference circuit comprises a first bipolar transistor having a base-emitter voltage V.sub.be1 and operated such that it has a constant operating current, and a second bipolar transistor having a base-emitter voltage V.sub.be2 and operated such that it has a
7251299 Time delay estimator July 31, 2007
A system for time delay estimation in a discrete time processing system includes a cross correlator that performs cross correlation on a first signal and a second signal, and provides a cross correlated output signals indicative thereof. A lag smoother receives the cross correlated o
7250885 System and method for using timing skew estimation with a non-sequential time-interleaved analog July 31, 2007
A multi-channel analog-to-digital converter system includes an array of sub-analog-to-digital converters wherein within the array of sub-analog-to-digital converters, there is at least one designated reference analog-to-digital converter. The analog-to-digital converter system also i
7250880 Analog to digital converter July 31, 2007
An analog to digital converter comprising at least two analog to digital conversion engines and a controller for controlling the operation of the analog to digital conversion engines such that during a first phase of an analog to digital conversion process the engines collaborate such th
7250819 Input tracking current mirror for a differential amplifier system July 31, 2007
An input tracking current mirror for a differential amplifier system includes a current mirror having an input leg and an output leg, a differential amplifier including a first set of at least two transconductance components, each having at least one input terminal for receiving inpu
7248661 Data transfer between phase independent clock domains July 24, 2007
An integrated circuit arrangement clocked by a single clock having variable delays to different regions of said arrangement such that said regions are partially synchronized to each other, the arrangement comprising: a data transfer buffer for buffering a data stream for transfer bet
7248646 Digital reconfigurable core for multi-mode base-band transmitter July 24, 2007
A reconfigurable communication transmitter core includes a digital pulse-shaping filter to perform pulse-shaping operations upon a digital modulated signal and a finite state machine to controls operation and reconfiguration of the digital pulse-shaping filter. A first memory stores
7248450 Pad cell with multiple signal paths July 24, 2007
An integrated circuit is described including internal circuitry and having at least one external connection. A pad cell is electrically interposed between the external connection and the internal circuitry, the pad cell comprising a first group of components adapted to protect the intern
7248192 Digital to analog converter and a ground offset compensation circuit July 24, 2007
A digital to analog converter comprising: a digital to analog conversion core adapted to receive at least one reference voltage and a digital word to be converted, and to output an analog voltage as a function of the digital word and the at least one reference voltage; a sensing circuit
7248035 Automatic test equipment pin channel with T-coil compensation July 24, 2007
A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably com
7245244 Correction methods and structures for analog-to-digital converter transfer functions July 17, 2007
Methods and structures are provided to improve the transfer functions of analog-to-digital converter systems. They address the converter error function that corresponds to a converter's transfer function. In particular, they provide a corrector with a corrector transfer function that
7242428 Image sensor using multiple array readout lines July 10, 2007
In one embodiment, an image sensor includes an area pixel array, column readout lines, and array readout lines, wherein the area pixel array includes columns of pixels, each including pixels of a first type, each column readout line is selectively coupled to outputs of the pixels of
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