| Patent Number |
Title Of Patent |
Date Issued |
| 6987314 |
Stackable semiconductor package with solder on pads on which second semiconductor package is sta |
January 17, 2006 |
| A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surfac |
| 6984879 |
Clamp for pattern recognition |
January 10, 2006 |
| A lead frame such as a normal or inverted lead frame includes an unsymmetrical part such as a gate. A clamp, for clamping the lead frame during wire bonding, includes an observation hole. The unsymmetrical part of the lead frame is visible through the observation hole. A lead eye box |
| 6982488 |
Semiconductor package and method for fabricating the same |
January 3, 2006 |
| A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The circuit board has a resin |
| 6982485 |
Stacking structure for semiconductor chips and a semiconductor package using it |
January 3, 2006 |
| A semiconductor package and method of producing the same has a substrate having a resin layer with first and second surfaces. A plurality of electrically conductive patterns are formed on the resin layer. An aperture is also formed at the center of the substrate. A first semiconducto |
| 6977431 |
Stackable semiconductor package and manufacturing method thereof |
December 20, 2005 |
| A stackable semiconductor package is disclosed that includes a semiconductor die coupled to a metal leadframe. The semiconductor die is coupled to a die pad and is electrically coupled to leads of the leadframe. The semiconductor die, the die pad, and an inner lead portion of each of |
| 6967395 |
Mounting for a package containing a chip |
November 22, 2005 |
| A mounting for a package containing a semiconductor chip is disclosed, along with methods of making such a mounting. The mounting includes a substrate having a mounting surface with conductive traces thereon, and an aperture extending through the substrate. The package includes a base, |
| 6967124 |
Imprinted integrated circuit substrate and method for imprinting an integrated circuit substrate |
November 22, 2005 |
| A die-attach method and assembly using film and epoxy bonds speeds manufacturing for large die assemblies while providing improved bond characteristics. An adhesive film defining an epoxy flow mask is attached to the die or substrate, epoxy is dispensed within the epoxy flow mask are |
| 6965159 |
Reinforced lead-frame assembly for interconnecting circuits within a circuit module |
November 15, 2005 |
| A lead-frame method and assembly for interconnecting circuits within a circuit module allows a circuit module to be fabricated without a circuit board substrate. Integrated circuit dies are attached to a metal lead-frame assembly and the die interconnects are wire-bonded to interconn |
| 6965157 |
Semiconductor package with exposed die pad and body-locking leadframe |
November 15, 2005 |
| A very thin, small outline, thermally enhanced semiconductor package includes a leadframe that is coined to form locking features on an exposed die pad and on a plurality of extremely narrow, closely spaced leads. The coined features improve the mechanical locking between the leadframe a |
| 6962829 |
Method of making near chip size integrated circuit package |
November 8, 2005 |
| A plurality of integrated circuit chip (IC chip) packages are fabricated simultaneously from a single insulating substrate having sections. In each section, an IC chip is attached. Bonding pads on the IC chip are electrically connected to first metallizations on a substrate first sur |
| 6956201 |
Image sensor package fabrication method |
October 18, 2005 |
| An image sensor package includes an image sensor, a window, and a molding, where the molding includes a lens holder extension portion extending upwards from the window. The lens holder extension portion includes a female threaded aperture extending from the window such that the window is |
| 6953988 |
Semiconductor package |
October 11, 2005 |
| A semiconductor package is disclosed that bonds a semiconductor chip to a leadframe using a flip chip technology. An exemplary semiconductor package includes a semiconductor chip having a plurality of input-output pads at an active surface thereof. A plurality of leads are superimposed b |
| 6946323 |
Semiconductor package having one or more die stacked on a prepackaged device and method therefor |
September 20, 2005 |
| A semiconductor package and method for producing the same has a substrate. A prepackaged semiconductor device is coupled to the substrate. At least one die is coupled to a top surface of the prepackaged semiconductor device. An adhesive layer is laid between the prepackaged semiconductor |
| 6946316 |
Method of fabricating and using an image sensor package |
September 20, 2005 |
| An image sensor package includes a molding having a locking feature. The package further includes a snap lid having a tab, where the tab is attached to the locking feature of the molding. To form the image sensor package, a window is placed in a pocket of the molding. The snap lid is |
| 6943429 |
Wafer having alignment marks extending from a first to a second surface of the wafer |
September 13, 2005 |
| A marked wafer includes a front-side surface and a back-side surface. A vertical scribe line and a horizontal scribe line are on the front-side surface of the wafer. A back-side alignment mark is located at an intersection of the vertical scribe line and the horizontal scribe line. T |
| 6936922 |
Semiconductor package structure reducing warpage and manufacturing method thereof |
August 30, 2005 |
| An electrical substrate useful for semiconductor packages is disclosed. The electrical substrate includes a core insulative layer. A first surface of the insulative layer has circuit patterns thereon. Some of the circuit patterns are stepped in their heights from the first surface, in th |
| 6930378 |
Stacked semiconductor die assembly having at least one support |
August 16, 2005 |
| A stack of semiconductor dies is disclosed. A first stack level includes a first semiconductor die and at least one first support that are attached to a substrate surface. A second level includes a second semiconductor die and at least one second support that are attached to the active s |
| 6930257 |
Integrated circuit substrate having laminated laser-embedded circuit layers |
August 16, 2005 |
| An integrated circuit substrate having laminated laser-embedded circuit layers provides a multi-layer high-density mounting and interconnect structure for integrated circuits. A prepared substrate, which may be a rigid double-sided dielectric or film dielectric with conductive patterns |
| 6930256 |
Integrated circuit substrate having laser-embedded conductive patterns and method therefor |
August 16, 2005 |
| An integrated circuit substrate having laser-embedded conductive patterns provides a high-density mounting and interconnect structure for integrated circuits. Conductive patterns within channels on the substrate provide interconnects that are isolated by the channel sides. A dielectric |
| 6927483 |
Semiconductor package exhibiting efficient lead placement |
August 9, 2005 |
| A semiconductor package exhibiting efficient placement of semiconductor leads in a micro lead frame design is provided. An integrated circuit die is bonded to the top surfaces of leads, thereby allowing the leads to partially reside under the die. As a result, surface area on the bottom |
| 6927478 |
Reduced size semiconductor package with stacked dies |
August 9, 2005 |
| A semiconductor package comprising a plurality of leads. Each of the leads defines opposed first and second surfaces, and a third surface which is also disposed in opposed relation to the second surface. The first surface is oriented between the second and third surfaces. The semiconduct |
| 6921967 |
Reinforced die pad support structure |
July 26, 2005 |
| A semiconductor package comprising a die pad defining opposed top and bottom surfaces and a peripheral edge. Attached to the peripheral edge of the die pad is a plurality of support feet which extend downwardly relative to the bottom surface thereof. A plurality of leads extend at le |
| 6919631 |
Structures for improving heat dissipation in stacked semiconductor packages |
July 19, 2005 |
| Semiconductor packages including at least two semiconductor dies are disclosed. A first die is mounted on a substrate, which may be a metallized laminate or a leadframe. A rigid support structure is mounted on the substrate over the first die. The support structure may be thermally c |
| 6919620 |
Compact flash memory card with clamshell leadframe |
July 19, 2005 |
| A memory card comprising a leadframe which includes a main frame defining a peripheral side. Extending toward the peripheral side of the main frame is a first set of leads, while extending away from the peripheral side is a second set of leads which are disposed in juxtaposed relation to |
| 6911718 |
Double downset double dambar suspended leadframe |
June 28, 2005 |
| In accordance with the present invention, there is provided a memory card which is fabricated through the use of a leadframe comprising an outer dambar defining a central opening, and an inner dambar which is disposed within the central opening. The leadframe further includes a plurality |
| 6910635 |
Die down multi-media card and method of making same |
June 28, 2005 |
| A circuit module comprising a leadframe having at least one die pad, a plurality of contacts, and a plurality of conductive traces extending from respective ones of the contacts toward the die pad. The traces are bent in a manner wherein the die pad and the contacts extend along respecti |
| 6905914 |
Wafer level package and fabrication method |
June 14, 2005 |
| A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric |
| 6900527 |
Lead-frame method and assembly for interconnecting circuits within a circuit module |
May 31, 2005 |
| A lead-frame method and assembly for interconnecting circuits within a circuit module allows a circuit module to be fabricated without a circuit board substrate. Integrated circuit dies are attached to a metal lead-frame assembly and the die interconnects are wire-bonded to interconn |
| 6897550 |
Fully-molded leadframe stand-off feature |
May 24, 2005 |
| A memory card comprising a leadframe having at least one die pad, a plurality of contacts, and a plurality of conductive traces extending from respective ones of the contacts toward the die pad. The traces are bent in a manner wherein the die pad and the contacts extend along respective |
| 6893900 |
Method of making an integrated circuit package |
May 17, 2005 |
| Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad |
| 6889813 |
Material transport method |
May 10, 2005 |
| A controlled material transport method for carrying materials to and from workstations, test equipment, and processing and assembly tools in a common facility. The present invention includes a rigid "robot vehicle" mountable to a passive track system, which can be routed to service all |
| 6888242 |
Color contacts for a semiconductor package |
May 3, 2005 |
| The surface of a solder ball and a conductive wire for a semiconductor package are coated with a predetermined colorant. Various colorants may be used according to the diameter and metal composition of the solder ball and the conductive wire. The colorant is formed by mixing organic comp |
| 6885086 |
Reduced copper lead frame for saw-singulated chip package |
April 26, 2005 |
| A lead frame strip for use in the manufacture of integrated circuit chip packages. The strip comprises at least one array defining a multiplicity of lead frames. The lead frames each include an outer frame defining a central opening having a die pad disposed therein. Attached to the oute |
| 6884695 |
Sheet resin composition and process for manufacturing semiconductor device therewith |
April 26, 2005 |
| A sheet resin composition is adhered to a silicon wafer. The sheet resin composition supports the silicon wafer during back grinding and dicing into chips. Further, the sheet resin composition interfacial underfills between a chip from the wafer and a substrate during subsequent fabr |
| 6879047 |
Stacking structure for semiconductor devices using a folded over flexible substrate and method t |
April 12, 2005 |
| A semiconductor stacking structure and method of producing the same has a flexible substrate. A plurality of apertures is formed on the flexible substrate. The plurality of apertures may be formed in groups for coupling semiconductor devices to the flexible substrate. A plurality of trac |
| 6879034 |
Semiconductor package including low temperature co-fired ceramic substrate |
April 12, 2005 |
| A semiconductor package comprising a low temperature co-fired ceramic substrate defining opposed top and bottom surfaces. The substrate comprises at least two stacked ceramic layers and electrically conductive patterns which extend between the layers and along the top surface of the |
| 6876068 |
Semiconductor package with increased number of input and output pins |
April 5, 2005 |
| In accordance with the present invention, there is provided a semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and including at least two slots formed therein and extending along respective ones of a pair of the peripheral edge |
| 6875379 |
Tool and method for forming an integrated optical circuit |
April 5, 2005 |
| Tools and methods for making molded an optical integrated circuit including one or more waveguides are disclosed. In one embodiment, a molding die is provided that includes a substrate that has a topographically patterned first surface. A conformal protective film is provided over the fi |
| 6873041 |
Power semiconductor package with strap |
March 29, 2005 |
| A semiconductor package and a method for fabricating a semiconductor package are disclosed. In one embodiment, the semiconductor package includes an exposed portion of a conductive strap at a package horizontal first surface and exposed surfaces of multiple leads at a package horizon |
| 6873032 |
Thermally enhanced chip scale lead on chip semiconductor package and method of making same |
March 29, 2005 |
| A thermally enhanced, chip-scale, Lead-on-Chip ("LOC") semiconductor package includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper |
| 6869861 |
Back-side wafer singulation method |
March 22, 2005 |
| A wafer includes a vertical scribe line and a horizontal scribe line on a front-side surface of the wafer. An intersection of the vertical scribe line and the horizontal scribe line is optically recognized through a wafer support attached to the front-side surface of the wafer. The wafer |
| 6867071 |
Leadframe including corner leads and semiconductor package using same |
March 15, 2005 |
| A leadframe comprising a frame body having four peripheral sides, each adjacent pair of which collectively defines a frame corner. Disposed within a central space or opening defined by the frame body is a die paddle including four peripheral edge segments, each adjacent pair of which |
| 6861720 |
Placement template and method for placing optical dies |
March 1, 2005 |
| A placement template and method for placing optical dies provides an alternative to large-die implementation for microelectromechanical systems (MEMS). Multiple dies are aligned by a template mounted on the substrate. Apertures in the template receive the dies and protrusions at the edge |
| 6858919 |
Semiconductor package |
February 22, 2005 |
| A semiconductor package is disclosed that bonds a semiconductor chip to a leadframe using a flip chip technology. An exemplary semiconductor package includes a semiconductor chip having a plurality of input-output pads at an active surface thereof. A plurality of leads are superimposed b |
| 6853060 |
Semiconductor package using a printed circuit board and a method of manufacturing the same |
February 8, 2005 |
| A semiconductor package has a substrate comprising a thermosetting resin layer of an approximate planar plate, a plurality of copper patterns formed at top and bottom surfaces of the resin layer, and protective layers coated on predetermined regions of the copper patterns and the the |
| 6853059 |
Semiconductor package having improved adhesiveness and ground bonding |
February 8, 2005 |
| A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package |
| 6849916 |
Flip chip on glass sensor package |
February 1, 2005 |
| An image sensor package includes an image sensor having an active area and bond pads on a front surface of the image sensor. A window is mounted to the image sensor by flip chip bumps formed between the bond pads of the image sensor and interior traces on an interior surface of the windo |
| 6847103 |
Semiconductor package with exposed die pad and body-locking leadframe |
January 25, 2005 |
| A very thin, small outline, thermally enhanced semiconductor package includes a leadframe that is coined to form locking features on an exposed die pad and on a plurality of extremely narrow, closely spaced leads. The coined features improve the mechanical locking between the leadframe a |
| 6847099 |
Offset etched corner leads for semiconductor package |
January 25, 2005 |
| A semiconductor package comprising a leadframe. The leadframe itself comprises an outer frame portion which defines a central opening. Disposed within the central opening is a die pad which defines opposed, generally planar top and bottom die pad surfaces and a peripheral edge. Connected |
| 6846704 |
Semiconductor package and method for manufacturing the same |
January 25, 2005 |
| A semiconductor package is provided which includes a semiconductor die having opposed, generally planar first and second surfaces and a peripheral edge. Formed on the second surface of the semiconductor die in close proximity to the peripheral edge thereof is a plurality of bond pads |
