| Patent Number |
Title Of Patent |
Date Issued |
| RE40112 |
Semiconductor package and method for fabricating the same |
February 26, 2008 |
| Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed. An embodiment of a semiconductor package includes a semiconductor chip having a first |
| 7399661 |
Method for making an integrated circuit substrate having embedded back-side access conductors an |
July 15, 2008 |
| A method for making an integrated circuit substrate having embedded back-side access conductors and vias provides a high-density mounting and interconnect structure for integrated circuits that is compatible with etched, plated or printed pre-manufactured substrate components. A circ |
| 7385408 |
Apparatus and method for testing integrated circuit devices having contacts on multiple surfaces |
June 10, 2008 |
| An apparatus and method which allows for testing a semiconductor device having contacts on multiple surfaces has a contactor assembly for holding a semiconductor device and for sending test signals from the test board to and from a first surface and a second surface of the semiconductor |
| 7375975 |
Enhanced durability memory card |
May 20, 2008 |
| In accordance with the present invention, there is provided multiple embodiments of a memory card, each embodiment including a case which is cooperatively engaged to a module comprising at least a printed circuit board having an electronic circuit device mounted thereto. In each embo |
| 7365006 |
Semiconductor package and substrate having multi-level vias fabrication method |
April 29, 2008 |
| A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of the circuit patter |
| 7362038 |
Surface acoustic wave (SAW) device package and method for packaging a SAW device |
April 22, 2008 |
| A surface acoustic wave (SAW) device package and method for packaging a SAW device provide a surface excited device having a small footprint, low cost and streamlined manufacturing process. A substrate including a SAW active area on a first side is interconnected to external circuits and |
| 7361533 |
Stacked embedded leadframe |
April 22, 2008 |
| A method of forming a stackable embedded leadframe package includes coupling an electronic component having bond pads to a substrate; coupling on the substrate a leadframe having a plurality of leads, each lead having a lower mounting portion; encapsulating the electronic component a |
| 7359579 |
Image sensor package and its manufacturing method |
April 15, 2008 |
| Disclosed are an image sensor package and a method for manufacturing the same. A sealing portion is formed between an image sensor die and a glass substrate to completely isolate the sensing portion of the image sensor die from external environment. Electrically conductive bumps are form |
| 7359204 |
Multiple cover memory card |
April 15, 2008 |
| A memory card including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto and at least one I/O pad and at least one test pad disposed thereon. The module is inserted into a complementary cavity formed within a case of the memory |
| 7358600 |
Interposer for interconnecting components in a memory card |
April 15, 2008 |
| A circuit module for use in a memory card. The circuit module comprises a base substrate including a plurality of contacts. Attached to the base substrate is a memory die, while attached to the memory die is an interposer having a plurality of terminals electrically connected to each |
| 7358174 |
Methods of forming solder bumps on exposed metal pads |
April 15, 2008 |
| A method of forming an electronic structure may include providing a substrate having a metal pad thereon. A conductive barrier layer may be formed on a first portion of the metal pad, and a second exposed portion of the metal pad may be free of the conductive barrier layer. In additi |
| 7342303 |
Semiconductor device having RF shielding and method therefor |
March 11, 2008 |
| A semiconductor device and method of manufacturing has a substrate having a plurality of metal layers. At least one metal layer is exposed on at least one side surface of the semiconductor device. A die is coupled to the substrate. A mold compound encapsulates the die and a top surface o |
| 7335986 |
Wafer level chip scale package |
February 26, 2008 |
| Disclosed is a wafer level chip scale package and a method for manufacturing the same. The wafer level chip scale package includes a semiconductor die having a first coating layer formed thereon; a redistribution layer formed on the first coating layer and connected to the bond pad; |
| 7334326 |
Method for making an integrated circuit substrate having embedded passive components |
February 26, 2008 |
| A method for making an integrated circuit substrate having embedded passive components provides a reduced cost and compact package for a die and one or more passive components. An insulating layer of the substrate is embossed or laser-ablated to generate apertures for insertion of a |
| 7332712 |
Camera module fabrication method including the step of removing a lens mount and window from the |
February 19, 2008 |
| An image sensor package includes an image sensor, a window, and a molding, where the molding includes a lens holder extension portion extending upwards from the window. The lens holder extension portion includes a female threaded aperture extending from the window such that the window |
| 7332375 |
Method of making an integrated circuit package |
February 19, 2008 |
| A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrica |
| 7322507 |
Transducer assembly, capillary and wire bonding method using the same |
January 29, 2008 |
| A transducer assembly and wire bonding method has a vibration unit for generating an ultrasonic wave. A body section is coupled to the vibration unit for transferring the ultrasonic wave. A tapered horn is coupled to the body section for transferring and concentrating the ultrasonic wave |
| 7321162 |
Semiconductor package having reduced thickness |
January 22, 2008 |
| A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in |
| 7317245 |
Method for manufacturing a semiconductor device substrate |
January 8, 2008 |
| Disclosed is a method for manufacturing a semiconductor device substrate. A substrate having no bus line and lead-in line is efficiently manufactured. In a step needing an electroplating process, conductive film is temporarily attached to circuit patterns in order to electrically con |
| 7312103 |
Method for making an integrated circuit substrate having laser-embedded conductive patterns |
December 25, 2007 |
| A method for making an integrated circuit substrate having laser-embedded conductive patterns provides a high-density mounting and interconnect structure for integrated circuits. A dielectric material is injection-molded or laminated over a metal layer that is punched or etched. The |
| 7297562 |
Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having emb |
November 20, 2007 |
| A circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns provides a high-density mounting and interconnect structure for semiconductor packages that is manufacturable in volume. A dielectric film is laminated on one o |
| 7293716 |
Secure digital memory card using land grid array structure |
November 13, 2007 |
| A memory card comprising a substrate which has a plurality of contacts and a plurality of metal features. The contacts and the metal features are disposed in spaced relation to each other and each define opposed first and second surfaces. Mounted to the substrate is at least one electron |
| 7253503 |
Integrated circuit device packages and substrates for making the packages |
August 7, 2007 |
| Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A planar metal die pad |
| 7247523 |
Two-sided wafer escape package |
July 24, 2007 |
| A method of forming an electronic component package includes: forming electrically conductive traces for connecting first selected bond pads of a plurality of bond pads on a first surface of an electronic component to corresponding bonding locations formed on a second surface of the |
| 7245007 |
Exposed lead interposer leadframe package |
July 17, 2007 |
| An interposer for use in an external lead or land pattern semiconductor package. The interposer includes an interposer body which is molded from a dielectric material. The interposer body defines opposed top and bottom surfaces, an outer peripheral edge, and an inner peripheral edge. |
| 7227236 |
Image sensor package and its manufacturing method |
June 5, 2007 |
| Disclosed are an image sensor package and its manufacturing method. As an example, an infrared ray protection glass is positioned directly on an image sensing region of an image sensor die. An electrically conductive wire and so forth located outside the image sensing region are enca |
| 7220915 |
Memory card and its manufacturing method |
May 22, 2007 |
| A memory card comprising a circuit board having opposed upper and lower circuit board surfaces, at least one test pad disposed on the upper circuit board surface, and a conductive pattern disposed on the lower circuit board surface and electrically connected to the test pad. Electric |
| 7217991 |
Fan-in leadframe semiconductor package |
May 15, 2007 |
| A semiconductor package comprising a plurality of elongate leads which each have opposed inner and outer ends, opposed first and second surfaces, and a third surface which is disposed in opposed relation to the first surface and recessed relative to the second surface. The second sur |
| 7214326 |
Increased capacity leadframe and semiconductor package using the same |
May 8, 2007 |
| In accordance with the present invention, there is provided a method for manufacturing a semiconductor package. The method comprises the initial step of applying first and second photoresist layers to respective ones of opposed first and second surfaces of a metal plate which includes a |
| 7211900 |
Thin semiconductor package including stacked dies |
May 1, 2007 |
| A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The circuit board has a resin |
| 7211879 |
Semiconductor package with chamfered corners and method of manufacturing the same |
May 1, 2007 |
| A semiconductor package comprising a die paddle defining multiple corners and opposed first and second surfaces. At least one set of leads extends at least partially about the die paddle in spaced relation thereto. Each of the leads has opposed first and second surfaces. Attached to and |
| 7211471 |
Exposed lead QFP package fabricated through the use of a partial saw process |
May 1, 2007 |
| A QFP exposed pad package which includes leads exposed within the bottom surface of the package body of the package in addition to those gull-wing leads protruding from the sides of the package body. Those leads exposed within the bottom surface of the package body are created through th |
| 7202554 |
Semiconductor package and its manufacturing method |
April 10, 2007 |
| A semiconductor package comprising paddle and a plurality of leads which extend at least partially about the die paddle in spaced relation thereto. Attached to the die paddle is a semiconductor die which is electrically connected to at least some of the leads. Attached to the semicon |
| 7201327 |
Memory card and its manufacturing method |
April 10, 2007 |
| A memory card comprising a die paddle having opposed, generally planar first and second die paddle surfaces and multiple peripheral edge segments. Disposed along and in spaced relation to one of the peripheral edge segments of the die paddle is a plurality of contacts, each of which |
| 7199359 |
Camera module fabrication method including singulating a substrate |
April 3, 2007 |
| An image sensor package includes an image sensor, a window, and a molding, where the molding includes a lens holder extension portion extending upwards from the window. The lens holder extension portion includes a female threaded aperture extending from the window such that the window |
| 7193305 |
Memory card ESC substrate insert |
March 20, 2007 |
| A memory card comprising a leadframe having a die pad, and an insert having a plurality of contacts. Attached to the die pad is a semiconductor die which is electrically connected to the contacts of the insert. A body covers the die pad and the semiconductor die and partially covers |
| 7192807 |
Wafer level package and fabrication method |
March 20, 2007 |
| A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric |
| 7190071 |
Semiconductor package and method for fabricating the same |
March 13, 2007 |
| There is provided a semiconductor package and method for fabricating the same. An embodiment of the semiconductor package includes: a semiconductor chip having a first face and a second face, the first face having a plurality of input/output pads formed thereon; a circuit board compo |
| 7190062 |
Embedded leadframe semiconductor package |
March 13, 2007 |
| A semiconductor package comprising a substrate having opposed top and bottom surfaces and a conductive pattern formed thereon. Disposed on the top surface of the substrate is a semiconductor die which is electrically connected to the conductive pattern. Also disposed on the top surface o |
| 7185426 |
Method of manufacturing a semiconductor package |
March 6, 2007 |
| A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an e |
| 7183630 |
Lead frame with plated end leads |
February 27, 2007 |
| A lead frame comprising a frame which defines a central opening. Disposed within the central opening is a die pad which is connected to the frame. Also connected to the frame are a plurality of leads which extend within the opening toward the die pad. Each of the leads defines opposed to |
| 7176062 |
Lead-frame method and assembly for interconnecting circuits within a circuit module |
February 13, 2007 |
| A lead-frame method and assembly for interconnecting circuits within a circuit module allows a circuit module to be fabricated without a circuit board substrate. Integrated circuit dies are attached to a metal lead-frame assembly and the die interconnects are wire-bonded to interconn |
| 7170183 |
Wafer level stacked package |
January 30, 2007 |
| Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically connected to a lower |
| 7170150 |
Lead frame for semiconductor package |
January 30, 2007 |
| A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include |
| 7154171 |
Stacking structure for semiconductor devices using a folded over flexible substrate and method t |
December 26, 2006 |
| A semiconductor stacking structure has a semiconductor device. A flexible substrate is coupled to a bottom surface of the semiconductor device. The flexible substrate is folded over on at least two sides to form flap portions. The flap portions are coupled to an upper surface of the firs |
| 7146106 |
Optic semiconductor module and manufacturing method |
December 5, 2006 |
| An optic semiconductor package includes a main board of a substantially planar plate shape. The main board includes an aperture therethrough and a plurality of board metal patterns formed at the periphery of the aperture. A package portion is coupled to the main board. The package po |
| 7145253 |
Encapsulated sensor device |
December 5, 2006 |
| Disclosed is a semiconductor device and its manufacturing method. By way of example, the semiconductor device includes a semiconductor die for sensing an external physical quantity, an insulating gel covering the semiconductor die, and an encapsulant which covers the insulating gel w |
| 7145251 |
Colored conductive wires for a semiconductor package |
December 5, 2006 |
| The surface of a solder ball and a conductive wire for a semiconductor package are coated with a predetermined colorant. Various colorants may be used according to the diameter and metal composition of the solder ball and the conductive wire. The colorant is formed by mixing organic |
| 7145238 |
Semiconductor package and substrate having multi-level vias |
December 5, 2006 |
| A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of the circuit patter |
| 7144517 |
Manufacturing method for leadframe and for semiconductor package using the leadframe |
December 5, 2006 |
| In accordance with the present invention, there is provided a method for manufacturing a leadframe. The method comprises the initial step of bonding a primary leadframe to an adhesive tape layer, the primary leadframe including a die paddle and a plurality of leads which extend at le |
