| Patent Number |
Title Of Patent |
Date Issued |
| RE40112 |
Semiconductor package and method for fabricating the same |
February 26, 2008 |
| Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed. An embodiment of a semiconductor package includes a semiconductor chip having a first |
| 7609461 |
Optical module having cavity substrate |
October 27, 2009 |
| A method of forming an optical module includes mounting an image sensor to a base of a substrate and bonding a lens housing to a sidewall of the substrate. A mounting surface of the lens housing includes a locking feature having a horizontal surface and a vertical surface. The sidewall |
| 7598598 |
Offset etched corner leads for semiconductor package |
October 6, 2009 |
| A semiconductor package comprising a leadframe. The leadframe itself comprises an outer frame portion which defines a central opening. Disposed within the central opening is a die pad which defines opposed, generally planar top and bottom die pad surfaces and a peripheral edge. Conne |
| 7589398 |
Embedded metal features structure |
September 15, 2009 |
| A method and structure for creating embedded metal features includes embedded trace substrates wherein bias and signal traces are embedded in a first surface of the embedded trace substrate and extend into the body of the embedded trace substrate. The bias trace and signal trace trenches |
| 7576401 |
Direct glass attached on die optical module |
August 18, 2009 |
| An optical module includes an image sensor having an active area and a window mounted directly to the image sensor above the active area. The optical module further includes a mount mounted to the window, the mount supporting a barrel having a lens assembly. By mounting the window di |
| 7572681 |
Embedded electronic component package |
August 11, 2009 |
| A method of forming an embedded electronic component package includes coupling a substrate to a first dielectric layer, strip, or panel, and forming first electrically conductive vias and traces in the first dielectric layer. A cavity is then formed in the first dielectric layer and |
| 7564122 |
Semiconductor package and method of making using leadframe having lead locks to secure leads to |
July 21, 2009 |
| A lead frame for making a semiconductor package is disclosed. The leadframe's leads include a lead lock provided at a free end of each inner lead that is adapted to increase a bonding force of the inner lead to a resin encapsulate, thereby effectively preventing a separation of the i |
| 7560804 |
Integrated circuit package and method of making the same |
July 14, 2009 |
| Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die |
| 7556986 |
Tape supported memory card leadframe structure |
July 7, 2009 |
| A method of fabricating a memory card. The method comprises the initial step of providing a leadframe which has a dambar and a plurality of contacts, each of the contacts being attached to the dambar by at least one tie bar. A layer of tape is applied to the leadframe such that the t |
| 7554194 |
Thermally enhanced semiconductor package |
June 30, 2009 |
| A semiconductor package has a substrate having a first surface, a second surface, and a through hole opening. A heat spreader has a first surface, a second surface, and a plurality of notches formed on the second surface. A semiconductor die is coupled to the first surface of the heat |
| 7550857 |
Stacked redistribution layer (RDL) die assembly package |
June 23, 2009 |
| A stacked redistribution layer (RDL) die assembly package includes a substrate, a first level RDL die assembly mounted to the substrate and a second level RDL die assembly mounted to the first level RDL die assembly. The first level RDL die assembly includes a first die comprising bo |
| 7548430 |
Buildup dielectric and metallization process and semiconductor package |
June 16, 2009 |
| A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive |
| 7535085 |
Semiconductor package having improved adhesiveness and ground bonding |
May 19, 2009 |
| A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the pac |
| 7521294 |
Lead frame for semiconductor package |
April 21, 2009 |
| A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include |
| 7507603 |
Etch singulated semiconductor package |
March 24, 2009 |
| In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventio |
| 7501338 |
Semiconductor package substrate fabrication method |
March 10, 2009 |
| An integrated circuit substrate having embedded lands with etching and plating control features provides improved manufacture of a high-density and low cost mounting and interconnect structure for integrated circuits. The integrated circuit substrate is formed by generating channels in a |
| 7485952 |
Drop resistant bumpers for fully molded memory cards |
February 3, 2009 |
| A memory card comprising a leadframe having a plurality of contacts, at least one die pad, and a plurality of conductive traces extending from respective ones of the contacts toward the die pad. Also included in the leadframe are at least two bumpers. Attached to the die pad is a sem |
| 7485491 |
Secure digital memory card using land grid array structure |
February 3, 2009 |
| A memory card comprising a substrate which has a plurality of contacts, at least one die pad, and a plurality of traces. The contacts, the die pad and the traces are disposed in spaced relation to each other and each define opposed first and second surfaces. Mounted to the first surface |
| 7485490 |
Method of forming a stacked semiconductor package |
February 3, 2009 |
| Disclosed is a stacking structure of semiconductor chips and semiconductor package using it, capable of achieving an electric insulation even if a conductive wire makes contact with a lower surface of an upper semiconductor chip, while reducing a total thickness thereof and preventin |
| 7473584 |
Method for fabricating a fan-in leadframe semiconductor package |
January 6, 2009 |
| A semiconductor package comprising a plurality of elongate leads which each have opposed inner and outer ends, opposed first and second surfaces, and a third surface which is disposed in opposed relation to the first surface and recessed relative to the second surface. The second sur |
| 7459776 |
Stacked die assembly having semiconductor die projecting beyond support |
December 2, 2008 |
| A stack of semiconductor dies is disclosed. A first stack level includes a first semiconductor die and at least one first support that are attached to a substrate surface. A second level includes a second semiconductor die and at least one second support that are attached to the active |
| 7459349 |
Method of forming a stack of semiconductor packages |
December 2, 2008 |
| A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surfac |
| 7446422 |
Wafer level chip scale package and manufacturing method for the same |
November 4, 2008 |
| Disclosed are a wafer level chip scale package and a method for manufacturing the same. An RDL is formed on a semiconductor die through a sputtering process, and a UBM is formed on the RDL through an electroplating process by using the RDL as a seed layer. Thus, the RDL sputtering, U |
| 7429799 |
Land patterns for a semiconductor stacking structure and method therefor |
September 30, 2008 |
| A semiconductor device has a substrate and an encapsulation area on a first surface of the substrate. A first plurality of metal lands is on the first surface of the substrate around a periphery of the encapsulation area. Solder mask covers portions of the first plurality of metal la |
| 7425750 |
Snap lid camera module |
September 16, 2008 |
| An image sensor package includes a molding having a locking feature. The package further includes a snap lid having a tab, where the tab is attached to the locking feature of the molding. To form the image sensor package, a window is placed in a pocket of the molding. The snap lid is |
| 7420272 |
Two-sided wafer escape package |
September 2, 2008 |
| A method of forming an electronic component package includes: forming electrically conductive traces for connecting first selected bond pads of a plurality of bond pads on a first surface of an electronic component to corresponding bonding locations formed on a second surface of the |
| 7399661 |
Method for making an integrated circuit substrate having embedded back-side access conductors an |
July 15, 2008 |
| A method for making an integrated circuit substrate having embedded back-side access conductors and vias provides a high-density mounting and interconnect structure for integrated circuits that is compatible with etched, plated or printed pre-manufactured substrate components. A circ |
| 7385408 |
Apparatus and method for testing integrated circuit devices having contacts on multiple surfaces |
June 10, 2008 |
| An apparatus and method which allows for testing a semiconductor device having contacts on multiple surfaces has a contactor assembly for holding a semiconductor device and for sending test signals from the test board to and from a first surface and a second surface of the semiconductor |
| 7375975 |
Enhanced durability memory card |
May 20, 2008 |
| In accordance with the present invention, there is provided multiple embodiments of a memory card, each embodiment including a case which is cooperatively engaged to a module comprising at least a printed circuit board having an electronic circuit device mounted thereto. In each embo |
| 7365006 |
Semiconductor package and substrate having multi-level vias fabrication method |
April 29, 2008 |
| A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of the circuit patter |
| 7362038 |
Surface acoustic wave (SAW) device package and method for packaging a SAW device |
April 22, 2008 |
| A surface acoustic wave (SAW) device package and method for packaging a SAW device provide a surface excited device having a small footprint, low cost and streamlined manufacturing process. A substrate including a SAW active area on a first side is interconnected to external circuits and |
| 7361533 |
Stacked embedded leadframe |
April 22, 2008 |
| A method of forming a stackable embedded leadframe package includes coupling an electronic component having bond pads to a substrate; coupling on the substrate a leadframe having a plurality of leads, each lead having a lower mounting portion; encapsulating the electronic component a |
| 7359579 |
Image sensor package and its manufacturing method |
April 15, 2008 |
| Disclosed are an image sensor package and a method for manufacturing the same. A sealing portion is formed between an image sensor die and a glass substrate to completely isolate the sensing portion of the image sensor die from external environment. Electrically conductive bumps are form |
| 7359204 |
Multiple cover memory card |
April 15, 2008 |
| A memory card including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto and at least one I/O pad and at least one test pad disposed thereon. The module is inserted into a complementary cavity formed within a case of the memory |
| 7358600 |
Interposer for interconnecting components in a memory card |
April 15, 2008 |
| A circuit module for use in a memory card. The circuit module comprises a base substrate including a plurality of contacts. Attached to the base substrate is a memory die, while attached to the memory die is an interposer having a plurality of terminals electrically connected to each |
| 7358174 |
Methods of forming solder bumps on exposed metal pads |
April 15, 2008 |
| A method of forming an electronic structure may include providing a substrate having a metal pad thereon. A conductive barrier layer may be formed on a first portion of the metal pad, and a second exposed portion of the metal pad may be free of the conductive barrier layer. In additi |
| 7342303 |
Semiconductor device having RF shielding and method therefor |
March 11, 2008 |
| A semiconductor device and method of manufacturing has a substrate having a plurality of metal layers. At least one metal layer is exposed on at least one side surface of the semiconductor device. A die is coupled to the substrate. A mold compound encapsulates the die and a top surface o |
| 7335986 |
Wafer level chip scale package |
February 26, 2008 |
| Disclosed is a wafer level chip scale package and a method for manufacturing the same. The wafer level chip scale package includes a semiconductor die having a first coating layer formed thereon; a redistribution layer formed on the first coating layer and connected to the bond pad; |
| 7334326 |
Method for making an integrated circuit substrate having embedded passive components |
February 26, 2008 |
| A method for making an integrated circuit substrate having embedded passive components provides a reduced cost and compact package for a die and one or more passive components. An insulating layer of the substrate is embossed or laser-ablated to generate apertures for insertion of a |
| 7332712 |
Camera module fabrication method including the step of removing a lens mount and window from the |
February 19, 2008 |
| An image sensor package includes an image sensor, a window, and a molding, where the molding includes a lens holder extension portion extending upwards from the window. The lens holder extension portion includes a female threaded aperture extending from the window such that the window |
| 7332375 |
Method of making an integrated circuit package |
February 19, 2008 |
| A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrica |
| 7322507 |
Transducer assembly, capillary and wire bonding method using the same |
January 29, 2008 |
| A transducer assembly and wire bonding method has a vibration unit for generating an ultrasonic wave. A body section is coupled to the vibration unit for transferring the ultrasonic wave. A tapered horn is coupled to the body section for transferring and concentrating the ultrasonic wave |
| 7321162 |
Semiconductor package having reduced thickness |
January 22, 2008 |
| A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in |
| 7317245 |
Method for manufacturing a semiconductor device substrate |
January 8, 2008 |
| Disclosed is a method for manufacturing a semiconductor device substrate. A substrate having no bus line and lead-in line is efficiently manufactured. In a step needing an electroplating process, conductive film is temporarily attached to circuit patterns in order to electrically con |
| 7312103 |
Method for making an integrated circuit substrate having laser-embedded conductive patterns |
December 25, 2007 |
| A method for making an integrated circuit substrate having laser-embedded conductive patterns provides a high-density mounting and interconnect structure for integrated circuits. A dielectric material is injection-molded or laminated over a metal layer that is punched or etched. The |
| 7297562 |
Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having emb |
November 20, 2007 |
| A circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns provides a high-density mounting and interconnect structure for semiconductor packages that is manufacturable in volume. A dielectric film is laminated on one o |
| 7293716 |
Secure digital memory card using land grid array structure |
November 13, 2007 |
| A memory card comprising a substrate which has a plurality of contacts and a plurality of metal features. The contacts and the metal features are disposed in spaced relation to each other and each define opposed first and second surfaces. Mounted to the substrate is at least one electron |
| 7253503 |
Integrated circuit device packages and substrates for making the packages |
August 7, 2007 |
| Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A planar metal die pad |
| 7247523 |
Two-sided wafer escape package |
July 24, 2007 |
| A method of forming an electronic component package includes: forming electrically conductive traces for connecting first selected bond pads of a plurality of bond pads on a first surface of an electronic component to corresponding bonding locations formed on a second surface of the |
| 7245007 |
Exposed lead interposer leadframe package |
July 17, 2007 |
| An interposer for use in an external lead or land pattern semiconductor package. The interposer includes an interposer body which is molded from a dielectric material. The interposer body defines opposed top and bottom surfaces, an outer peripheral edge, and an inner peripheral edge. |
