| Patent Number |
Title Of Patent |
Date Issued |
| 6294936 |
Spread-spectrum modulation methods and circuit for clock generator phase-locked loop |
September 25, 2001 |
| A spread-spectrum modulation method and circuit for a clock generator phase-locked loop (PLL). A dither signal is injected into a PLL in synchronization with and having the same period or fraction of the same period as the phase comparison performed within the PLL. Over such period, |
| 6271539 |
Electrical diagnostic technique for silicon plasma-etch induced damage characterization |
August 7, 2001 |
| Characterization of plasma-induced damage in semiconductor manufacturing has long been considered unimportant because the damage had no discernable effect on circuit performance. With increasing transistor counts on an integrated circuit, the damage-induced parasitics are becoming in |
| 6265729 |
Method for detecting and characterizing plasma-etch induced damage in an integrated circuit |
July 24, 2001 |
| Characterization of plasma-induced damage in semiconductor manufacturing has long been considered unimportant because the damage had no discernible effect on circuit performance. With increasing transistor counts on an integrated circuit, the damage-induced parasitics are becoming in |
| 5923609 |
Strobed wordline driver for fast memories |
July 13, 1999 |
| A wordline driver for a semiconductor memory array having a circuit for selecting and deselecting the first end of an addressed wordline and a circuit for deselecting the second end of the addressed wordline. The first and second ends of the addressed wordline are deselected at subst |
| 5838168 |
3V/5V input buffer |
November 17, 1998 |
| An input buffer capable of operating at a first power supply voltage level or a second power supply voltage level with the operating voltage level selectable during manufacture. At least one shortable transistor is disposed between the power supply voltage input and a buffer circuit whic |
| 5838046 |
Operating method for ROM array which minimizes band-to-band tunneling |
November 17, 1998 |
| A read only memory (ROM) array is disclosed which includes a) a voltage supply providing an operating voltage level, b) a plurality of word-lines, c) a multiplicity of ROM transistors, and d) a word-line clamper. The ROM transistors are divided into turned on and turned off transistors. |
| 5683925 |
Manufacturing method for ROM array with minimal band-to-band tunneling |
November 4, 1997 |
| A method of manufacturing a ROM array to minimize band-to-band tunneling is described. The method includes the steps of: a) implanting bit lines into the core area of a substrate as per a later-removed bit line mask, b) providing a ROM oxide layer over the entirety of the substrate, c) e |
| 5682353 |
Self adjusting sense amplifier clock delay circuit |
October 28, 1997 |
| A clock delay circuit for generating a delay for a sense amplifier release signal in an integrated circuit semiconductor memory device is disclosed. Rather than utilize traditional programmable capacitors that must be trimmed on a die by die basis, the novel clock delay circuit disclosed |
| 5663675 |
Multiple stage tracking filter using a self-calibrating RC oscillator circuit |
September 2, 1997 |
| A multiple stage tracking filter includes a self-calibrating RC oscillator, a resistor connected to the self-calibrating RC oscillator and a capacitor connected to the self-calibrating RC oscillator. The filter further includes a switched capacitor filter element connected to the sel |
| 5617062 |
Timing circuit with rapid initialization on power-up |
April 1, 1997 |
| A timer initialization circuit is used to stabilize a timing signal of a system timed using a core oscillator. The timer initialization circuit includes a circuit which disables the core oscillator during a power-down mode and re-enables the core oscillator upon termination of the power- |
| 5594388 |
Self-calibrating RC oscillator |
January 14, 1997 |
| An RC oscillator includes an RC network for forming a time constant equal to the RC product. However, this RC time constant is not used in the manner of a typical RC network to set the frequency of oscillation. Instead, the RC oscillator disclosed herein includes a separate oscillato |
| 5589802 |
Circuit for detecting the absence of an external component |
December 31, 1996 |
| A component detector circuit operates to detect the presence or absence of a circuit component, such as an external component. A resistor detecting circuit includes a biasing circuit connected to the resistor. The biasing circuit generating a bias current. The resistor detecting circuit |
| 5585765 |
Low power RC oscillator using a low voltage bias circuit |
December 17, 1996 |
| A low power RC oscillator includes a low power bias circuit and an RC network. The RC network is used to form a time constant equal to the RC product. However, this RC time constant is not used in the manner of a typical RC network to set the frequency of oscillation. Instead, the RC |
| 5552748 |
Digitally-tuned oscillator including a self-calibrating RC oscillator circuit |
September 3, 1996 |
| A digitally-tuned oscillator (DTO) includes a digital-to-analog converter (DAC) and an RC oscillator. The RC oscillator includes an RC circuit for forming a time constant equal to the RC product. However, this RC time constant is not used in the manner of a typical RC network to set the |
| 5521556 |
Frequency converter utilizing a feedback control loop |
May 28, 1996 |
| A monolithic frequency converter using a feedback control loop generates a source of synthesized frequency signals over a wide dynamic range based on a timing source such as a crystal oscillator or an external frequency source. The frequency converter includes a controlled oscillator, a |
| 4894565 |
Asynchronous digital arbiter |
January 16, 1990 |
| An asynchronous digital arbiter circuit suitable for use in computer systems applications requiring fast asynchronous arbitration between two asynchronous inputs. The arbiter resolves which of two input signals is to be granted access, and provides a busy signal to the source of the othe |
| 4853759 |
Integrated circuit filter with reduced die area |
August 1, 1989 |
| An electronic filter which has particular application for use as an antialiasing filter in sampled data systems fabricated so as to utilize high resistivity diffused regions (36, 37) within the semiconductor body (31), as opposed to low resistivity polycrystalline silicon resistors. |
| 4807972 |
Temperature compensating driver for a liquid crystal display |
February 28, 1989 |
| A circuit (8) is provided for driving the segment and back plane of a liquid crystal display. The circuit includes a plurality of transistors (Q1 to Q10) connected such that the base emitter junctions of the transistors are coupled in series between a voltage source and ground. The v |
| 4764691 |
CMOS programmable logic array using NOR gates for clocking |
August 16, 1988 |
| A programmable logic array 100 which uses parallel transistor logic gates 150 arranged in a compact layout for fast signal propagation. One of logic planes 120 or 130 is prechargeable to substantially reduce power consumption using a simple, one-phase clock. |
| 4757359 |
Thin oxide fuse |
July 12, 1988 |
| An oxide fuse, and method of forming same, formed by a thin layer of oxide dielectric between a lower electrode substrate and an upper electrode. A fuse-programming bias of approximately 15V causes Fowler-Nordheim tunneling at low temperature to damage the dielectric layer, and shorts |
| 4756080 |
Metal foil semiconductor interconnection method |
July 12, 1988 |
| A single layer copper foil tape is provided having a center core and connected lead beams. Etched apertures are formed to separate adjacent lead beams and to form relatively high strength foil straps connecting edge portions of the foil tape and the center core. Score lines may be et |
| 4720034 |
Apparatus and method of solder coating integrated circuit leads |
January 19, 1988 |
| Desired control of the thickness and composition of a solder coat on the J-leads of an integrated circuit Quad package is obtained by orienting the packages while being solder coated in a "leads-up" orientation as a series of strips mounting the packages are passed through a solder wave |
| 4717868 |
Uniform intensity led driver circuit |
January 5, 1988 |
| A unique driver circuit for providing constant average current through a driven element or elements having varying impedance first samples the impedance at the drive terminal in order to determine impedance of the driven elements. For increasing impedance of the driven elements, the duty |
| 4716586 |
State sequence dependent read only memory |
December 29, 1987 |
| The addresses of firmward (ROM) being interrogated to ascertain data are continuously monitored. Selected key addresses are recognized by address detection means. Timing means is then actuated to count a preset number of address accesses, system clock cycles, or other suitable timing mea |
| 4698617 |
ROM Protection scheme |
October 6, 1987 |
| The present apparatus provides for the encoding of data carried on bus lines running between integrated circuits in order to protect the data carried upon those bus lines, with encoding and decoding circuits included for providing those functions in regard to the data on the bus lines. |
| 4673933 |
Switch matrix encoding interface using common input/output parts |
June 16, 1987 |
| An encoding interface is provided between input data ports and strobe output ports of a (semiconductor integrated) circuit (chip) and an array of switches (40) is connected to a series of L input data lines and output lines (31-38), whereby the L lines can alternatively strobe the switch |
| 4657172 |
Apparatus and method of solder coating integrated circuit leads |
April 14, 1987 |
| Desired control of the thickness and composition of a solder coat on the J-leads of an integrated circuit Quad package is obtained by orienting the packages while being solder coated in a "leads-up" orientation as a series of strips mounting the packages are passed through a solder wave |
| 4644504 |
Programmable CMOS circuit for user defined chip enable and output enable |
February 17, 1987 |
| A circuit constructed in accordance with this invention is described which includes a programmable chip enable-output enable buffer (11-X). The chip enable-output enable buffer may be programmed to provide a chip enable function in response to a logical 1 or logical 0 chip enable input s |
| 4636721 |
Method and structure for testing high voltage circuits |
January 13, 1987 |
| A unique method and structure is provided for testing high voltage equipment with great accuracy of voltage levels to be measured, repeatability of measured levels from one piece of test equipment to the next, no need for recalibration of test equipment, and sufficiently low current |
| 4635002 |
Metal oxide semiconductor logarithmic voltage controlled oscillator |
January 6, 1987 |
| Voltage controlled oscillator (50) provides an exponential transfer function. The frequency of the output signal of the voltage controlled oscillator varies exponentially with the input voltages (V.sub.IN1, V.sub.IN2) to the oscillator. The exponential transfer characteristic is prov |
| 4633220 |
Decoder using pass-transistor networks |
December 30, 1986 |
| A matrix comprised of pass transistor cells (81 through 96) forms an address decoder circuit (80). By using pass transistor cells in a matrix format, a decoder which consumes a minimum of power and which may be constructed using a minimum of allotted space in an integrated circuit is |
| 4631429 |
High voltage compressing input buffer |
December 23, 1986 |
| A circuit (40) is capable of receiving a very high voltage input signal, for example from a piezoelectric transducer (1). The circuit accepts the relatively large input voltage of the piezoelectric transducer (1) and provides an output signal proportional to the square root of the input |
| 4629909 |
Flip-flop for storing data on both leading and trailing edges of clock signal |
December 16, 1986 |
| A flip-flop stores input data on both the leading and trailing edges of a clock pulse. The flip-flop includes a data path responsive to the leading edge of a clock pulse and a second data path responsive to the trailing edge of a clock pulse, thereby allowing data to be stored on both th |
| 4622648 |
Combinational logic structure using PASS transistors |
November 11, 1986 |
| PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected control signals, thereby to generate a selected output function on the output node. The |
| 4596954 |
Frequency doubler with fifty percent duty cycle output signal |
June 24, 1986 |
| A unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifier, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers constructed in accordance with the |
| 4594577 |
Current mirror digital to analog converter |
June 10, 1986 |
| An integrated circuit digital to analog converter comprised of MOS current mirrors and utilizing additional MOS devices to provide transmission gates and control means. Each transmission gate 36 is connected to a source of digital data to be converted and the mirroring device for each |
| 4590457 |
Digital to analog converter utilizing pulse width modulation |
May 20, 1986 |
| A pulse width digital to analog converter is constructed which provides an output clock rate that is a multiple of the input sampling rate. In one embodiment a latch is used to store N-bit digital word representing the analog signal value to be generated. (N-K) of the most significant bi |
| 4590440 |
Phase locked loop with high and/or low frequency limit detectors for preventing false lock on ha |
May 20, 1986 |
| A phase locked loop circuit (16) includes means to eliminate harmonic frequency locking. The phase locked loop includes a voltage controlled oscillator (1) which provides an output signal (V.sub.out) which is compared with the input signal (V.sub.in) by a phase detector (4). The outp |
| 4580065 |
Single-shot circuit having process independent duty cycle |
April 1, 1986 |
| A single-shot circuit is fabricated as an integrated circuit except for a single capacitor requiring a single pin to connect to the on-chip circuitry. The single-shot is rendered independent of process variations and operating conditions by incorporating an analog feedback loop. The |
| 4566064 |
Combinational logic structure using PASS transistors |
January 21, 1986 |
| PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node. The |
| 4555668 |
Gain amplifier |
November 26, 1985 |
| A novel switched capacitor gain stage uses a unique circuit design and clocking technique that reduces the component mismatch offset voltage and the clock-induced feedthrough offset voltage produced by the circuit. The total capacitance ratio between the input capacitors and the feedback |
| 4541103 |
Digitally controlled syllabic filter for a delta modulator |
September 10, 1985 |
| A unique CVSD CODEC is provided utilizing switched capacitor technology. This CVSD CODEC includes a syllabic filter which provides one of a large number of possible step sizes, thereby allowing the CVSD CODEC to accurately track and convert a wide range of input voltages. The CVSD CO |
| 4541067 |
Combinational logic structure using PASS transistors |
September 10, 1985 |
| PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node. The |
| 4540949 |
Reference voltage circuit including a three-terminal operational amplifier with offset compensat |
September 10, 1985 |
| An operational amplifier has one noninverting input lead (116), and two inverting input leads (117a, 117b). One of these inverting input leads (117a) is utilized to compensate for the effects of the inherent offset voltage (V.sub.off) of the operational amplifier, and the second invertin |
| 4533876 |
Differential operational amplifier with common mode feedback |
August 6, 1985 |
| A differential operational amplifier is provided with a feedback loop which continuously adjusts the common mode voltage level of the amplifier so that it lies in the center of the dynamic range of the amplifier. The feedback loop measures the instantaneous common mode voltage level and |
| 4490629 |
High voltage circuits in low voltage CMOS process |
December 25, 1984 |
| A CMOS push-pull output buffer (171) is constructed utilizing a plurality of N channel transistors (74, 75, 76) and a plurality of P channel transistors (71, 72, 73) connected in series. The voltages applied to the gates of the N channel transistors and P channel transistors are selected |
| 4475170 |
Programmable transversal filter |
October 2, 1984 |
| A programmable transversal filter utilizes a plurality of programmable multiplying means. The result of each multiplication is summed by a summing circuit, thus providing an output signal. The delay network comprises a plurality of signal sample and hold circuits which are selectivel |
| 4470126 |
Programmable transversal filter |
September 4, 1984 |
| A programmable transversal filter (10) utilizes a plurality of programmable multiplying means (M.sub.1 -M.sub.4). The result of each multiplication is summed by a summing circuit (7), thus providing an output signal (y(t)). The delay network of this invention comprises a plurality of sam |
| 4468798 |
Dual charge pump envelope generator |
August 28, 1984 |
| A switched capacitor filter is designed utilizing two switched capacitor charge pumps connected in series. These two charge pumps operate with different clock frequencies thereby allowing charging of a storage capacitor at a higher frequency, thereby decreasing incremental voltage st |
| 4466172 |
Method for fabricating MOS device with self-aligned contacts |
August 21, 1984 |
| A method for fabricating an integrated circuit semiconductor device comprised of an array of MOSFET elements having self-aligned or self-registered connections with conductive interconnect lines. The method involves the formation on a substrate of a thick oxide insulation layer (30) |
