| Patent Number |
Title Of Patent |
Date Issued |
| RE40894 |
Sample and load scheme for observability internal nodes in a PLD |
September 1, 2009 |
| A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data p |
| RE40883 |
Methods and apparatus for dynamic instruction controlled reconfigurable register file with exten |
August 25, 2009 |
| A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many |
| RE40509 |
Methods and apparatus for abbreviated instruction sets adaptable to configurable processor archi |
September 16, 2008 |
| An improved manifold array (ManArray) architecture addresses the problem of configurable application-spacific instruction set optimization and instruction memory reduction using an instruction abbreviation process thereby further optimizing the general ManArray architecture for appli |
| RE40213 |
Methods and apparatus for providing direct memory access control |
April 1, 2008 |
| Techniques are described for providing mechanisms of data distribution to and collection of data from multiple memories in a data processing system. The system may suitably be a manifold array (ManArray) processing system employing an array of processing elements. Virtual to physical |
| RE40011 |
System for coupling programmable logic device to external circuitry which selects a logic standa |
January 22, 2008 |
| A programmable input/output device for use with a programmable logic device (PLD) is presented comprising an input buffer, an output buffer and programmable elements. The programmable elements may be programmed to select a logic standard for the input/output device to operate at. For |
| RE38651 |
Variable depth and width memory device |
November 9, 2004 |
| A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal |
| RE38451 |
Universal logic module with arithmetic capabilities |
March 2, 2004 |
| A universal logic module for use in a programmable logic device, capable of generating all logical functions of three variables or less. The universal logic module also implements a full adder with carry propagation. |
| RE37060 |
Apparatus for serial reading and writing of random access memory arrays |
February 20, 2001 |
| A method of serially reading and writing random access memory arrays is provided. Although the read/write inputs continually change as programming data are clocked into the input buffers, a read/write control circuit prevents the constantly changing read/write inputs from causing undesir |
| RE35977 |
Look up table implementation of fast carry arithmetic and exclusive-or operations |
December 1, 1998 |
| Look up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is effectively partitioned into smaller look up tables when an adder or counter is required. |
| D510916 |
Housing having shape embedded circuit board |
October 25, 2005 |
|
| D508897 |
Embedded circuit board |
August 30, 2005 |
|
| D508026 |
Chip and light emitting diode panel housing |
August 2, 2005 |
|
| D507783 |
Embedded circuit board housing |
July 26, 2005 |
|
| 7620925 |
Method and apparatus for performing post-placement routability optimization |
November 17, 2009 |
| A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. Optimizing placement of the system for routing is performed after placing the system. The system is routed after optimizing placement. |
| 7620876 |
Reducing false positives in configuration error detection for programmable devices |
November 17, 2009 |
| A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. |
| 7620853 |
Methods for detecting resistive bridging faults at configuration random-access memory output nod |
November 17, 2009 |
| Integrated circuits such as programmable logic device integrated circuits have configuration random-access memory elements. The configuration random-access memory elements are tested to determine whether any of the elements have resistive bridging faults at their outputs. During testing, |
| 7619460 |
Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling |
November 17, 2009 |
| A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, |
| 7619451 |
Techniques for compensating delays in clock signals on integrated circuits |
November 17, 2009 |
| Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an |
| 7619443 |
Programmable logic device architectures and methods for implementing logic in those architecture |
November 17, 2009 |
| A programmable logic device ("PLD") architecture includes logic elements ("LEs") grouped together in clusters called logic array blocks (LABs"). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as |
| 7616657 |
Heterogeneous transceiver architecture for wide range programmability of programmable logic devi |
November 10, 2009 |
| High-speed serial data transceiver circuitry on a programmable logic device ("PLD") includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high |
| 7613991 |
Method and apparatus for concurrent calculation of cyclic redundancy checks |
November 3, 2009 |
| Circuits and methods provide the concurrent calculation of CRC bits for messages from different channels, where one part of a message is received at a time. Context buffers store certain state variables of the CRC calculation for each channel. The context buffers output data in a syn |
| 7613858 |
Implementing signal processing cores as application specific processors |
November 3, 2009 |
| Methods and apparatus are provided for efficiently implementing signal processing cores as application specific processors. A signal processing core, such as a Fast Fourier Transform (FFT) core or a Finite Impulse Response (FIR) core includes a data path and a control path. A control |
| 7613760 |
Efficient implementation of multi-channel integrators and differentiators in a programmable devi |
November 3, 2009 |
| Efficiently implemented multi-channel integrators and multi-channel differentiators utilize a delay section in a single integrator or differentiator in lieu of parallel integrator or differentiator lines to handle multi-channel data flow and processing. The delay section functions li |
| 7613263 |
Clock and data recovery method and apparatus |
November 3, 2009 |
| A method and circuit for processing a serial data stream carrying data at a rate established by an underlying clock signal, the method and circuit involving: time-stamping each of the transitions of a sequence of transitions within the serial data stream to thereby generate a sequence |
| 7613055 |
Programmable control block for dual port SRAM application |
November 3, 2009 |
| A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between |
| 7612410 |
Trigger device for ESD protection circuit |
November 3, 2009 |
| The present invention is a trigger device useful, for example, in triggering an SCR in an ESD protection circuit. Illustratively, an NMOS trigger device comprises a gate and heavily doped P and N regions in a P-well on opposite sides of the gate. A first N type source/drain extension |
| 7607118 |
Techniques for using edge masks to perform timing analysis |
October 20, 2009 |
| Techniques are provided for more efficient timing analysis of user designs for programmable ICs. Initially, a graph is created that represents nodes and edges in a user design. Each edge in the graph is assigned a binary edge mask, each bit of which indicates whether it is reachable from |
| 7606362 |
FPGA configuration bitstream encryption using modified key |
October 20, 2009 |
| Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is m |
| 7606248 |
Method and apparatus for using multiple network processors to achieve higher performance network |
October 20, 2009 |
| An apparatus is described having a plurality of network processors that identify, for each of a plurality of packets, which multidimensional queue from amongst a plurality of multidimensional queues that each one of the plurality of packets should be enqueued into. Each of the network |
| 7606081 |
Device programmable to operate as a multiplexer, demultiplexer, or memory device |
October 20, 2009 |
| A device that is programmable to operate as a memory device, a multiplexer, or a demultiplexer includes: a first column decoder; a memory array coupled to the first column decoder; a plurality of selectors coupled to the memory array; and a second column decoder coupled to the plural |
| 7605603 |
User-accessible freeze-logic for dynamic power reduction and associated methods |
October 20, 2009 |
| A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic |
| 7602634 |
Dynamic RAM storage techniques |
October 13, 2009 |
| Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell |
| 7602260 |
Programmable supply voltage regulator for oscillator |
October 13, 2009 |
| A circuit comprises a programmable voltage regulator and an oscillator. The programmable regulator generates a regulated supply voltage using an input voltage and changes the regulated supply voltage from a first voltage to a second voltage in response to a first control signal. The |
| 7602255 |
Loop circuits that reduce bandwidth variations |
October 13, 2009 |
| A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump |
| 7602212 |
Flexible high-speed serial interface architectures for programmable integrated circuit devices |
October 13, 2009 |
| An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes high-speed serial data signal interface channels, some of which include more circuitry that is dedicated to performing various high-speed ser |
| 7602062 |
Package substrate with dual material build-up layers |
October 13, 2009 |
| Multi-layered, organic build-up semiconductor package substrates have build-up layers with layers of both fibrous organic dielectric material and non-fibrous organic dielectric material. Non-fibrous dielectric material layers are positioned below the signal metal layers and fibrous d |
| 7598790 |
Clock synthesis using polyphase numerically controlled oscillator |
October 6, 2009 |
| A clock synthesis circuit includes a polyphase numerically controlled oscillator, an extraction circuit, and a clock signal generation circuit. The polyphase numerically controlled oscillator generates sets of periodic output signals. Each set of the periodic output signals represent |
| 7598779 |
Dual-mode LVDS/CML transmitter methods and apparatus |
October 6, 2009 |
| A dual-mode LVDS/CML transmitter allows a single circuit to operate as either an LVDS transmitter or a CML transmitter. The transmitter mode can be switched by activating or deactivating appropriate circuit elements, and changing the voltage or current produced by appropriate sources or |
| 7598769 |
Apparatus and method for a programmable logic device having improved look up tables |
October 6, 2009 |
| A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2.sup.N configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2.sup.N |
| 7598767 |
Multi-standard data communication interface circuitry for programmable logic devices |
October 6, 2009 |
| A programmable logic device includes a hard IP portion, which includes circuitry that is dedicated to receiving a high-speed serial data signal and performing certain basic functions related to byte alignment on that data signal, and a more general-purpose programmable logic portion. The |
| 7594208 |
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum perf |
September 22, 2009 |
| Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that |
| 7594204 |
Method and apparatus for performing layout-driven optimizations on field programmable gate array |
September 22, 2009 |
| A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A first copy and a second copy of the group of components are generated where the first copy |
| 7593499 |
Apparatus and method for low power routing of signals in a low voltage differential signaling sy |
September 22, 2009 |
| A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displ |
| 7593334 |
Method of policing network traffic |
September 22, 2009 |
| According to one embodiment, a method of regulating traffic at a network hardware machine is disclosed. The method includes receiving a data packet, calculating a time stamp difference value, determining whether a maximum token bucket value has been exceeded by the time stamp difference |
| 7593273 |
Read-leveling implementations for DDR3 applications on an FPGA |
September 22, 2009 |
| Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving |
| 7592832 |
Adjustable transistor body bias circuitry |
September 22, 2009 |
| An integrated circuit is provided that contain n-channel and p-channel metal-oxide-semiconductor transistors having body terminals. Adjustable transistor body bias circuitry is provided on the integrated circuit that provides body bias voltages to the body terminals to minimize power |
| 7590879 |
Clock edge de-skew |
September 15, 2009 |
| Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further embodiment of the presen |
| 7590676 |
Programmable logic device with specialized multiplier blocks |
September 15, 2009 |
| A specialized multiplier block in a programmable logic device incorporates multipliers and adders, and is configurable as one or more types of finite impulse response (FIR) filter including a Direct Form II FIR filter. The specialized multiplier block further includes input and outpu |
| 7590211 |
Programmable logic device integrated circuit with communications channels having sharing phase-l |
September 15, 2009 |
| Integrated circuits such as programmable logic device integrated circuits are provided that have resource-efficient receiver circuitry. In source-synchronous system environments, an integrated circuit receives data on multiple buses, each of which has a reference clock signal and ass |
| 7590207 |
Modular serial interface in programmable logic device |
September 15, 2009 |
| A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabli |
