| Patent Number |
Title Of Patent |
Date Issued |
| RE40923 |
Simplified data link protocol processor |
September 29, 2009 |
| A simplified data link protocol which may be implemented in a very high-speed transmission system, e.g., SONET, processes a datagram received from an IP facility according to QoS considerations and scrambles a datagram before it is again scrambled by a transmission system, e.g., a SO |
| RE40032 |
Wireless data communication system having power saving function |
January 22, 2008 |
| A wireless data communication system is operable in a power saving mode wherein stations are synchronized to be in an awake state to receive synchronizing messages (TIM, PSYNC) and traffic indicator information and are changed to a doze state if they are not to receive data messages. In |
| 7617467 |
Electrostatic discharge device verification in an integrated circuit |
November 10, 2009 |
| Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit; identifying ESD devices based at least in part on the input dataset; extracting devices |
| 7616686 |
Method and apparatus for generating one or more clock signals for a decision-feedback equalizer |
November 10, 2009 |
| Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. |
| 7613061 |
Method and apparatus for idle cycle refresh request in DRAM |
November 3, 2009 |
| Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed by determining if a refresh of the dynamic random access memory is required; and allocatin |
| 7612592 |
Programmable duty-cycle generator |
November 3, 2009 |
| A duty-cycle generator including, in one embodiment, a duty-cycle adjustment circuit and a delay processor. The duty-cycle adjustment circuit is adapted to receive an input clock signal having an input duty cycle, generate first and second versions of the input clock signal having di |
| 7610568 |
Methods and apparatus for making placement sensitive logic modifications |
October 27, 2009 |
| Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already placed chip design to meet functional requirements of an engineering change. The already |
| 7610507 |
High-speed redundant disk controller methods and systems |
October 27, 2009 |
| Various apparatus and methods for controlling data for a redundant array of inexpensive/independent disks (RAID) are presented. For example, in one illustrative embodiment, a controlling apparatus can include a translation device composed substantially entirely of gate-level electron |
| 7610495 |
Method and apparatus for power management using transmission mode with reduced power |
October 27, 2009 |
| A method and apparatus are disclosed for power management of an electronic device. The present invention reduces power consumption of an electronic device that communicates over a network by selecting a transmission mode with reduced power consumption as the battery level gets lower. A |
| 7610444 |
Method and apparatus for disk address and transfer size management |
October 27, 2009 |
| A method includes storing first and second sets of parameters in a register. Each set of parameters defines a storage transaction to store data to a computer readable medium or a retrieval transaction to retrieve data from the computer readable medium. The first storage or retrieval |
| 7609097 |
Driver circuit and a method for matching the output impedance of a driver circuit with a load im |
October 27, 2009 |
| A line driver circuit with an output impedance that is set to a value which is based at least in part on the impedance of one or more current sources of the driver circuit. The current source impedance varies depending on the desired output amplitude of the driver circuit. Once the c |
| 7607112 |
Method and apparatus for performing metalization in an integrated circuit process |
October 20, 2009 |
| A reverse fill pattern is used in an integrated circuit (IC) that comprises a metal layer having slots formed therein in the shape of rhombuses. The distribution of rhombic slots ensures that electrical current is evenly distributed in the conductor, even at the edge regions of the c |
| 7607072 |
Method and apparatus for-soft-output viterbi detection using a multiple-step trellis |
October 20, 2009 |
| Methods and apparatus are provided for performing Soft-Output Viterbi Algorithm (SOVA) detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through |
| 7607065 |
Method and apparatus for block and rate independent decoding of LDPC codes |
October 20, 2009 |
| Methods and apparatus are provided for block and rate independent decoding of LDPC codes. The disclosed LDPC decoders support multiple code block lengths and code rates, as well as a variable parity check matrix. The disclosed LDPC decoders decode LDPC codes that are based on a parity |
| 7606317 |
Channel optimization system |
October 20, 2009 |
| A channel optimization system for use with a communications channel and method of separating and encoding signals associated with the communications channel. In one embodiment, the channel optimization system includes an assorter that receives first and second signals having disparat |
| 7606302 |
Method and apparatus for non-linear decision-feedback equalization in the presence of asymmetric |
October 20, 2009 |
| Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization in the presence of a non-linear channel. A latch employed by a decision-feedback equalizer is positioned by constraining input data such that the i |
| 7606301 |
Method and apparatus for adaptively establishing a sampling phase for decision-feedback equaliza |
October 20, 2009 |
| Methods and apparatus are provided for adaptively establishing the optimal sampling phase offset for a DFE operation. According to one aspect of the invention, one or more values in an amplitude domain are converted into a time domain, for example, using a phase detector, based on phase |
| 7606233 |
Method for micro-controller and DSP based data communication within a transceiver |
October 20, 2009 |
| The present invention provides a method for improved data communication and a transceiver employing the method. In one embodiment, the method includes generating data blocks to transmit to a second transceiver, generating identification data for the data blocks and identifying the da |
| 7606222 |
System and method for increasing the range or bandwidth of a wireless digital communication netw |
October 20, 2009 |
| A system and method, associated with a receiver, for increasing the range or bandwidth of a wireless digital communication network and a receiver incorporating the system or the method. In one embodiment, the system includes: (1) a service class detector configured to determine a service |
| 7605064 |
Selective laser annealing of semiconductor material |
October 20, 2009 |
| A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient ene |
| 7603468 |
Home adaptive transceiver for home networking communication system |
October 13, 2009 |
| A self calibrating network comprises a first node and a second node. The first node transmits a calibration data packet. The second node receives the calibration data packet and determines a calibration value for the second node to optimize the transfer of data from the first node to the |
| 7599461 |
Method and apparatus for generating one or more clock signals for a decision-feedback equalizer |
October 6, 2009 |
| Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data, in the presence of an adverse pattern, such as a Nyquist pattern. A received signal is sampled using a data clock and a transition clock to generate a |
| 7599364 |
Configurable network connection address forming hardware |
October 6, 2009 |
| An apparatus and method are provided for extracting connection information from a traffic header in a communications network. The apparatus includes a first storage element containing a first look-up table for determining a first data packet header offset and data size for extracting a |
| 7598815 |
Multiple frequency generator for quadrature amplitude modulated communications |
October 6, 2009 |
| Multiple carrier frequencies are provided from a phase locked loop, especially closely adjacent quadrature amplitude modulated subcarriers for multiplexed data communications. A quadrature voltage controlled oscillator (VCO) and cascaded frequency dividers provide feedback to a phase |
| 7598602 |
Controlling warping in integrated circuit devices |
October 6, 2009 |
| Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a |
| 7596779 |
Condition management callback system and method of operation thereof |
September 29, 2009 |
| A condition management callback system and method for use with a processor employing a hierarchical register consolidation structure. In one embodiment, the system includes: (1) a condition management structure, (2) a callback abstraction subsystem configured to register a callback f |
| 7596147 |
Apparatus and method for fractional processing of cells in a communications system |
September 29, 2009 |
| At least one cell in a communications system, from a network side, is caused to be stored into a cell buffer bulk memory. Responsive to detecting a predetermined fullness condition of a timeslot memory buffer, a predetermined number of bytes (corresponding to a fraction of the payloa |
| 7595951 |
Head-specific standby modes for disk drive preamplifiers and the like |
September 29, 2009 |
| A (e.g., hard-disk drive (HD)) system supports reader standby mode and/or writer standby mode. For reader standby mode, reader circuitry in the system's preamplifier is transitioned to a low-power mode during write operations. To provide quick transition from write mode to read mode, the |
| 7595569 |
Versatile and intelligent power controller |
September 29, 2009 |
| The invention provides a monolithic, highly integrated power supply circuit capable of providing various voltages for circuits on an expansion card, either from a main supply source or an auxiliary supply source. The monolithic power supply circuit preferably includes two switching c |
| 7593831 |
Method and apparatus for testing delay lines |
September 22, 2009 |
| Disclosed is a circuit for testing a delay module. An output of a ring oscillator formed with the delay module is transmitted to a counter. The counter generates a plurality of counts, each count associated with a setting of control lines of the delay module. One of the plurality of |
| 7593529 |
Scramble methods and apparatus for packetized digital video signal in conditional access system |
September 22, 2009 |
| A conditional access scrambling or encryption technique for a packetized digital data stream, e.g., a MPEG-2 bitstream, (1) by scrambling or encrypting the data payload of selective transport payload packets (e.g., every nth packet); (2) by scrambling or encrypting only a portion (e.g., |
| 7593498 |
Method and apparatus for automatic rate identification and channel synchronization in a master-s |
September 22, 2009 |
| Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use between a parallel bus and a serial bus. The interface includes a plurality of serializer |
| 7593479 |
Precoding for a non-linear codec |
September 22, 2009 |
| A preceding system to achieve rates higher than 33.6 kbps in the analog modem to digital modem direction. The preceding system modifies the standard THP algorithm to adapt it for use in PCM modems. The present invention overcomes the above-described difficulties by preceding an upstr |
| 7593327 |
Method and apparatus for frequency offset control of ethernet packets over a transport network |
September 22, 2009 |
| A method and apparatus are disclosed for compensating for a frequency offset between an ingress local area network and an egress local area network that communicate over a transport network. The bandwidth of an egress port is adjusted by varying an inter-packet gap size between each |
| 7593269 |
Differential flash memory programming technique |
September 22, 2009 |
| The invention relates flash memory programming techniques. An object of the invention is to provide a flash memory programming technique avoiding problems of the known state of the art and in particular, saving a significant amount of time during the development and/or production pha |
| 7590961 |
Integrated circuit with signal skew adjusting cell selected from cell library |
September 15, 2009 |
| An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal in the digital circuitry of the integrated circuit to a desired amount. The digital logi |
| 7590118 |
Frame aggregation format |
September 15, 2009 |
| A frame format for frame aggregation into a physical-layer packet employs an aggregated frame descriptor appended to one or more sub-frames. Each sub-frame comprises a header comprising logical-layer and sub-frame protocol information, optional verification information to verify the |
| 7590056 |
Processor configured for efficient processing of single-cell protocol data units |
September 15, 2009 |
| A processor includes controller circuitry configurable to determine for a given packet or other protocol data unit (PDU) received by the processor whether the given PDU is a single-cell PDU. If the given PDU is a single-cell PDU, information characterizing the given PDU is stored in |
| 7587657 |
Method and apparatus for iterative error-erasure decoding |
September 8, 2009 |
| Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at le |
| 7587640 |
Method and apparatus for monitoring and compensating for skew on a high speed parallel bus |
September 8, 2009 |
| Methods and apparatus are provided for monitoring and compensating for skew on a high speed parallel bus. Delay skew for a plurality of signals on a parallel bus is monitored by obtaining a plurality of samples of the plurality of signals for each unit interval; and identifying a locatio |
| 7587549 |
Buffer management method and system with access grant based on queue score |
September 8, 2009 |
| A method includes assigning each of a plurality of disk write and disk read requests to respective ones of a plurality of queues. Each queue has an occupancy level and a weight. A score is assigned to each of the plurality of queues, based on the occupancy and weight of the respective |
| 7586948 |
Packet sub-frame structure for selective acknowledgment |
September 8, 2009 |
| A wireless local area network includes transmission of data packets between endpoints in which packet frames are divided into sub-frames. On reception of a frame, the integrity of each individual sub-frame is checked. Sub-frames that pass the integrity check are acknowledged and retr |
| 7586909 |
Striping algorithm for switching fabric |
September 8, 2009 |
| A striping algorithm selects a route on which to transmit each next data segment, in dependence upon relative channel loading so far, taking account of multicast. Input modules can keep a channel loading history for each route it has, and can update its history for each route that a |
| 7586704 |
Method and apparatus for improving threshold detection of servo data in the presence of signal a |
September 8, 2009 |
| An adaptive asymmetry control circuit is described. Such a circuit may be used in magnetic recording applications, for example. The adaptive asymmetry control circuit uses a peak detector which supplies at regular intervals positive or negative signal peak values of an equalized sampled |
| 7584439 |
Cell modeling for integrated circuit design with characterization of upstream driver strength |
September 1, 2009 |
| A cell is modeled for use in an integrated circuit design by characterizing the cell based on an input of the cell being driven by a characterization driver having a specified drive strength. A model of the cell is generated which stores an identifier of the characterization driver i |
| 7583805 |
Late reverberation-based synthesis of auditory scenes |
September 1, 2009 |
| A scheme for stereo and multi-channel synthesis of inter-channel correlation (ICC) (normalized cross-correlation) cues for parametric stereo and multi-channel coding. The scheme synthesizes ICC cues such that they approximate those of the original. For that purpose, diffuse audio cha |
| 7583762 |
Reduced-complexity multiple-input, multiple-output detection |
September 1, 2009 |
| A wireless receiver detects signals generated with a multiple-input, multiple-output (MIMO) transmitter. The receiver applies maximum-likelihood detection (MLD) for soft-output signal detection, where an MLD exhaustive search across all candidate vectors is performed recursively by c |
| 7583582 |
M-ary orthogonal keying system |
September 1, 2009 |
| A digital modulation system provides enhanced multipath performance by using modified orthogonal codes with reduced autocorrelation sidelobes while maintaining the cross-correlation properties of the modified codes. For example, the modified orthogonal codes can reduce the autocorrelatio |
| 7583458 |
Channel optimization metrics |
September 1, 2009 |
| A recording system, such as a magnetic or optical recording system, employs optimization metrics that are independent of a target partial response for equalization of a signal read from a recording channel. The optimization metrics employ samples adjacent to codeword boundaries of co |
| 7583153 |
Systems and methods for multiplexing multiphase clocks |
September 1, 2009 |
| Various embodiments of the present invention provide systems, circuits and methods that allow for switching between two or more multiphase clocks. As one example, a system for switching between multiphase clocks is disclosed. The system includes a multiphase clock multiplexer. The mu |
