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Advanced Micro Devices, Inc. Patents
Advanced Micro Devices, Inc.
Austin, TX
No. of patents:

Patent Number Title Of Patent Date Issued
RE39518 Run to run control process for controlling critical dimensions March 13, 2007
It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforw
RE35794 System for reducing delay for execution subsequent to correctly predicted branch instruction usi May 12, 1998
A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate
D661667 Socket assembly June 12, 2012
D658607 Circuit package lid May 1, 2012
D648688 Socket housing November 15, 2011
D645426 Socket assembly September 20, 2011
D641720 Circuit package lid July 19, 2011
D633880 Socket housing March 8, 2011
D633879 Socket cap March 8, 2011
D633878 Socket cover cap March 8, 2011
D633877 Socket frame March 8, 2011
8589670 Adjusting system configuration for increased reliability based on margin November 19, 2013
A system provides a mechanism for increasing reliability by allowing margins to be evaluated and if one or more margins of a current configuration are too small, system configuration is modified to increase the margin. A computing device determines through training a first operating
8589661 Odd and even start bit vectors November 19, 2013
A method and apparatus are presented for processing a stream of information, including preprocessing the stream, which includes partitioning the stream into packets of interest; determining boundaries for the packets of interest, wherein a packet boundary is either a start location o
8589629 Method for way allocation and way locking in a cache November 19, 2013
A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) de
8589627 Partially sectored cache November 19, 2013
The present invention provides embodiments of a partially sectored cache. One embodiment of the apparatus includes a cache that includes a tag array for storing information indicating a plurality of tags and a data array for storing a plurality of lines. A first portion of the tags have
8587600 System and method for cache-based compressed display data storage November 19, 2013
Systems and methods for cache-based compressed display data storage are provided. One system includes memory operable to store compressed display data, a processor comprising a processing core and a cache, a cache storage module operably coupled to the memory and the processor, wherein
8587049 Memory cell system with charge trap November 19, 2013
A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.
8586981 Silicon-on-insulator ("SOI") transistor test structure for measuring body-effect November 19, 2013
According to one exemplary embodiment, a silicon-on-insulator (SOI) transistor test structure includes a gate situated over a semiconductor body and a doped halo under the gate. The SOI transistor test structure further includes at least two semiconductor body contacts situated on op
8585877 Multi-step deposition control November 19, 2013
For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each set of process par
8584067 Clock domain crossing buffer November 12, 2013
Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where
8584065 Method and apparatus for designing an integrated circuit November 12, 2013
A method and apparatus for designing an integrated circuit to operate at a desired clock frequency range reduces process variation by estimating the value of removable pessimism from a static timing analysis. The pessimism includes, for example, at least one of the removable on-chip-
8583971 Error detection in FIFO queues using signature bits November 12, 2013
A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read
8580660 Double and triple gate MOSFET devices and methods for making same November 12, 2013
A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a fir
8578141 Loop predictor and method for instruction fetching using a loop predictor November 5, 2013
A loop predictor and a method for instruction fetching using a loop predictor. A processor may include a loop predictor in addition to a primary branch predictor. A relatively common scenario in program execution is that a set of branches repeat over and over forming a loop. The loop
8578129 Infrastructure support for accelerated processing device memory paging without operating system November 5, 2013
In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; r
8576924 Piecewise processing of overlap smoothing and in-loop deblocking November 5, 2013
A video processing apparatus and methodology are implemented as a combination of a processor and a video decoding hardware block to decode video data by performing piecewise processing of overlap smoothing and in-loop deblocking in a macroblock-based fashion. With this approach, a sm
8576236 Mechanism for granting controlled access to a shared resource November 5, 2013
Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned
8575972 Digital frequency synthesizer device and method thereof November 5, 2013
A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third an
8575029 Technique for forming metal lines in a semiconductor by adapting the temperature dependence of t November 5, 2013
By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanc
8574965 Semiconductor chip device with liquid thermal interface material November 5, 2013
A method of manufacturing is provided that includes providing a semiconductor chip device that has a circuit board and a first semiconductor chip coupled thereto. A lid is placed on the circuit board. The lid includes an opening and an internal cavity. A liquid thermal interface mate
8573841 On-chip temperature sensor November 5, 2013
A method and apparatus for determining a temperature of a semiconductor device is provided herein. One aspect of the disclosed subject matter is seen in a temperature sensing device. The temperature sensing device comprises a diode and a circuit. The diode is adapted to be reverse bi
8570881 Transmitter voltage and receiver time margining October 29, 2013
A technique for characterizing a communications interface includes determining a voltage margin and a timing margin of the interface based on data sampled by a sampling device of a receiver of the interface. In at least one embodiment of the invention, a method for determining margin
8570783 Low power content-addressable memory and method October 29, 2013
Content-Addressable Memory (CAM) arrays and related circuitry for integrated circuits and CAM array comparison methods are provided such that relatively low power is used in the operation of the CAM circuitry. A binary value pair is stored in a pair of CAM memory elements. A comparis
8570113 Digital VCO calibration method and apparatus October 29, 2013
A method and circuitry for calibrating the gain of a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a comparator configured to provide a first indication if the VCO gain is not within the specified gain range, and a second indication if the VC
8570090 Electronic component protection power supply clamp circuit October 29, 2013
Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrost
8570067 Method and apparatus for controlling a communication signal by monitoring one or more voltage so October 29, 2013
An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp
8566645 Debug state machine and processor including the same October 22, 2013
A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace
8566628 North-bridge to south-bridge protocol for placing processor in low power state October 22, 2013
A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Br
8566570 Distributed multi-core memory initialization October 22, 2013
In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a pl
8566382 Method and apparatus for improved calculation of multiple dimension fast fourier transforms October 22, 2013
Apparatus and methods for storing data in a block to provide improved accessibility of the stored data in two or more dimensions. The data is loaded into memory macros constituting a row of the block such that sequential values in the data are loaded into sequential memory macros. Th
8564583 Bias circuit for a complementary current mode logic drive circuit October 22, 2013
A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit
8564347 Phase detector circuit for automatically detecting 270 and 540 degree phase shifts October 22, 2013
Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system
8564326 Circuit and method to control slew rate of a current-mode logic output driver October 22, 2013
A method is provided for selecting at least one of a plurality of slew rate control settings based at least upon a speed of data transmission and receiving input data where the input data is received at the data transmission speed. The method also includes switching the received input
8564122 Circuit board component shim structure October 22, 2013
Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first
8564041 Contacts for semiconductor devices October 22, 2013
A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from
8301672 GPU assisted garbage collection October 30, 2012
A system and method for efficient garbage collection. A general-purpose central processing unit (CPU) sends a garbage collection request and a first log to a special processing unit (SPU). The first log includes an address and a data size of each allocated data object stored in a heap in
8299633 Semiconductor chip device with solder diffusion protection October 30, 2012
Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip that has a substrate and a first active circuitry portion extending a firs
8298924 Method for differential spacer removal by wet chemical etch process and device with differential October 30, 2012
By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channe
8294731 Buffer management in vector graphics hardware October 23, 2012
A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edg
8294266 Conductor bump method and apparatus October 23, 2012
Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric

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