| Patent Number |
Title Of Patent |
Date Issued |
| RE39518 |
Run to run control process for controlling critical dimensions |
March 13, 2007 |
| It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforw |
| RE35794 |
System for reducing delay for execution subsequent to correctly predicted branch instruction usi |
May 12, 1998 |
| A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate |
| 7620470 |
Method and apparatus for impasse detection and resolution |
November 17, 2009 |
| A method, apparatus and a system, for provided for performing an automated process flow adjustment. A semiconductor wafer is processed based upon a routing plan and a predetermined schedule. A fault detection relating to the processing of the semiconductor wafer is performed. Dynamically |
| 7618755 |
Method and system for automatically detecting exposed substrates having a high probability for d |
November 17, 2009 |
| By automatically estimating the focus status of individual substrates or lots on the basis of focus-specific tool information obtained from the exposure tool, such as tilt angle ranges used during the automatic focusing procedures, possible hot spot errors may be detected highly effi |
| 7617404 |
In-band power management in a communication link |
November 10, 2009 |
| A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more trainin |
| 7616021 |
Method and device for determining an operational lifetime of an integrated circuit device |
November 10, 2009 |
| An integrated circuit device includes a degradable test structure, a first external interface pin and a second external interface pin, a first conductive path coupling a first node of the degradable test structure and the first external interface pin, and a second conductive path cou |
| 7615103 |
Apparatus and method for removing bubbles from a process liquid |
November 10, 2009 |
| The present invention is directed to methods and apparatuses for removing bubbles from a process liquid. The process liquid can comprise a plating solution used in a plating tool. The process liquid is supplied to a tank. A plurality of streams of the process liquid are directed towards |
| 7613821 |
Arrangement for reducing application execution based on a determined lack of flow control credit |
November 3, 2009 |
| An InfiniBand.TM. network node includes a network interface, a system memory, a memory controller configured for controlling access to the system memory, and a processor. The network interface is configured for outputting data packets according to a prescribed flow control protocol t |
| 7613534 |
Web based semiconductor ordering architecture |
November 3, 2009 |
| A semiconductor fabrication architecture which includes a middleware component, a fabrication facility coupled to the middleware component, a real time dispatcher application program interface coupled between the fabrication facility and the middleware component, a work in progress a |
| 7613266 |
Binary controlled phase selector with output duty cycle correction |
November 3, 2009 |
| A phase selection circuit having a selection circuit, binary weighted current sources, and an amplifier circuit. The phase selection circuit is configured for selecting adjacent phase signals from a number of equally-spaced phases of a clock signal, based on a phase selection value. |
| 7613237 |
Built-in test feature to facilitate system level stress testing of a high-speed serial link that |
November 3, 2009 |
| A method of ensuring robust operation of a differential serial link is provided. The method provides a first integrated circuit having 1) a phase generator constructed and arranged to provide a programmable shift of a clock signal based on selective interpolating between first and se |
| 7611991 |
Technique for increasing adhesion of metallization layers by providing dummy vias |
November 3, 2009 |
| By providing dummy vias below electrically non-functional metal regions, the risk for metal delamination in subsequent processes may be significantly reduced. Moreover, in some embodiments, the mechanical strength of the resulting metallization layers may be even more enhanced by pro |
| 7611935 |
Gate straining in a semiconductor device |
November 3, 2009 |
| Gate straining techniques as described herein can be utilized during the fabrication of NMOS transistor devices, PMOS transistor devices, or CMOS device structures. For an NMOS device, conductive vias are formed in TEOS oxide regions surrounding the sidewall spacers of a metal gate struc |
| 7610476 |
Multiple control sequences per row of microcode ROM |
October 27, 2009 |
| Various embodiments of methods and systems for storing multiple groups of microcode operations and corresponding control sequences per row of microcode ROM are disclosed. In one embodiment, an integrated circuit may include a microcode ROM coupled to a control sequence logic unit. The |
| 7609190 |
Device and method for testing of digital-to-analog converter |
October 27, 2009 |
| A current-steering digital-to-analog converter (DAC) is tested using a test component having a relaxation oscillator with an oscillation frequency based on the output current of the DAC. A series of test values is provided in sequence to the DAC for conversion to an output current wi |
| 7608912 |
Technique for creating different mechanical strain in different CPU regions by forming an etch s |
October 27, 2009 |
| The present invention provides a technique for reducing stress or stress gradients in highly sensitive device regions, such as cache areas, while still providing high transistor performance in logic areas by correspondingly providing contact etch stop layers with compressive and tens |
| 7608501 |
Technique for creating different mechanical strain by forming a contact etch stop layer stack ha |
October 27, 2009 |
| By partially removing an etch stop layer prior to the formation of a first contact etch stop layer, a superior stress transfer mechanism may be provided in an integration scheme for generating strain by means of contact etch stop layers. Thus, a semiconductor device having different |
| 7608499 |
Semiconductor structure comprising field effect transistors with stressed channel regions and me |
October 27, 2009 |
| A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. Each of the first transistor element and the second transistor element comprises a gate electrode. A stressed material la |
| 7607031 |
Power management in a communication link |
October 20, 2009 |
| A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters a training phase in which training p |
| 7606985 |
Augmented instruction set for proactive synchronization within a computer system |
October 20, 2009 |
| Providing proactive synchronization in a computer system may include providing an augmented instruction set with additional synchronizing instructions. Therefore, a method includes a processor executing a set of instructions to request exclusive access to a plurality of memory resour |
| 7606976 |
Dynamically scalable cache architecture |
October 20, 2009 |
| A technique for managing power consumption of a cache memory system dynamically adjusts the size of the cache memory system according to an energy level of an energy storage device. In at least one embodiment of the invention, an apparatus includes a dynamically scalable cache memory |
| 7605045 |
Field effect transistors and methods for fabricating the same |
October 20, 2009 |
| Field effect transistors and methods for fabricating field effect transistors are provided. A method, in accordance with an exemplary embodiment of the invention, comprises forming a polycrystalline silicon gate electrode overlying a silicon substrate. The gate electrode has two para |
| 7604903 |
Mask having sidewall absorbers to enable the printing of finer features in nanoprint lithography |
October 20, 2009 |
| A mask is provided to be used with nanoprint lithography processes to facilitate reproduction of small features required for the production of integrated circuits. A translucent substrate is provided along with one or more three-dimensional features that include one or more vertical |
| 7603551 |
Initialization of a computer system including a secure execution mode-capable processor |
October 13, 2009 |
| The initialization of a computer system including a secure execution mode-capable processor includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory. The method also includes exe |
| 7603550 |
Computer system including a secure execution mode-capable CPU and a security services processor |
October 13, 2009 |
| A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includ |
| 7598161 |
Method of forming transistor devices with different threshold voltages using halo implant shadow |
October 6, 2009 |
| The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally orie |
| 7596803 |
Method and system for generating access policies |
September 29, 2009 |
| A method and system for generating security rules for implementation by a rule interpretation engine to define accessibility to one or more aspects of an Enterprise System is described. The method and system allow a security officer to graphically indicate an operation to be affected by |
| 7596742 |
Error detection in a communication link |
September 29, 2009 |
| A communication protocol that allows an inserted control packet to immediately follow another control packet can be more robust to single bit errors when the two types of control packets can be distinguished using transmitted control signals to perform packet framing without having t |
| 7595269 |
Semiconductor device comprising a copper alloy as a barrier layer in a copper metallization laye |
September 29, 2009 |
| By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis |
| 7592258 |
Metallization layer of a semiconductor device having differently thick metal lines and a method |
September 22, 2009 |
| A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to |
| 7590309 |
Image processing in integrated circuit technology development |
September 15, 2009 |
| An image processing system provides a method for processing an image including classifying the image, comparing the image to stored images, storing the image if the image does not match one of the stored images, and storing a link to a stored image if the image matches one of the sto |
| 7586153 |
Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors |
September 8, 2009 |
| By forming a strained semiconductor layer in a PMOS transistor, a corresponding compressively strained channel region may be achieved, while, on the other hand, a corresponding strain in the NMOS transistor may be relaxed. Due to the reduced junction resistance caused by the reduced |
| 7586059 |
Lithography mask substrate labeling system |
September 8, 2009 |
| A substrate labeling system includes a first laser assembly having a first laser and a first lens, a second laser assembly having a second laser and a second lens, and a controller for directing the first laser and the second laser incident on a portion of a subsurface of a substrate to |
| 7585759 |
Technique for efficiently patterning an underbump metallization layer using a dry etch process |
September 8, 2009 |
| By patterning the underbump metallization layer stack on the basis of a dry etch process, significant advantages may be achieved compared to conventional techniques involving a highly complex wet chemical etch process. In particular embodiments, a titanium tungsten layer or any other |
| 7584237 |
Fast hardware divider |
September 1, 2009 |
| A method and mechanism for performing division. A processor includes a divider configured to perform arithmetic division operations. Prior to dividing a dividend by a divisor, the divider manipulates the dividend and divisor to reduce the number of bits considered and the computations |
| 7583833 |
Method and apparatus for manufacturing data indexing |
September 1, 2009 |
| A method, apparatus, and a system for generating an index for storing data. A pattern associated with a first set of data is determined. The first set of data is stored. A determination is made as to whether the pattern associated with a second set of data corresponds to the pattern |
| 7582493 |
Distinguishing between dopant and line width variation components |
September 1, 2009 |
| A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the |
| 7581140 |
Initiating test runs based on fault detection results |
August 25, 2009 |
| A method and apparatus are provided for initiating test runs based on a fault detection result. The method comprises receiving operational data associated with processing of a workpiece by a processing tool, processing the operational data to determine fault detection results; and ca |
| 7580519 |
Triple DES gigabit/s performance using single DES engine |
August 25, 2009 |
| Security processing circuits are discussed which may be used alone or as part of a network interface device of a host system using a single DES engine to accomplish 3DES processing. The security processing circuit is adapted for selectively encrypting outgoing data and decrypting incomin |
| 7579262 |
Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same |
August 25, 2009 |
| By omitting a growth mask or by omitting lithographical patterning processes for forming growth masks, a significant reduction in process complexity may be obtained for the formation of different strained semiconductor materials in different transistor types. Moreover, the formation |
| 7576771 |
Method and apparatus of providing video synchronization |
August 18, 2009 |
| Video control signals are received at a video input port of a system. A determination is made whether the video control signals are valid or invalid. When video control signals represent a valid video signal, providing a delayed representation of a control signal to a synchronization |
| 7576357 |
System for characterization of low-k dielectric material damage |
August 18, 2009 |
| A method of detecting damage to at least one dielectric layer in an IC die by determining a capacitance factor. The capacitance factor can be used to determine damage in a low-k dielectric material. A system for detecting damage can include a conductive line structure for measuring c |
| 7572705 |
Semiconductor device and method of manufacturing a semiconductor device |
August 11, 2009 |
| A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion |
| 7571318 |
Method and apparatus for improved security in a data processor |
August 4, 2009 |
| A method and apparatus for controlling access to segments of memory having security data stored therein is provided. A security check unit maintains information for a plurality of segments of memory regarding whether each of these plurality of segments has secure data stored therein. A h |
| 7571020 |
Method and system for controlling process tools by interrupting process jobs depending on job pr |
August 4, 2009 |
| By enabling an interleaved mode when supplying substrates from a plurality of load ports to a respective process module, a reduction of non-productive time of the process tool and/or a reduction of cycle time may be achieved compared to a conventional sequential processing of carrier |
| 7569937 |
Technique for forming a copper-based contact layer without a terminal metal |
August 4, 2009 |
| By directly forming an underbump metallization layer on a copper-based contact region, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers may be avoided. Consequently, the thermal and electrical behavior of the resulting bump struct |
| 7569437 |
Formation of transistor having a strained channel region including a performance enhancing mater |
August 4, 2009 |
| By forming a semiconductor alloy in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device performance of advanc |
| 7568134 |
Method of exhaustively testing an embedded ROM using generated ATPG test patterns |
July 28, 2009 |
| A model of the memory device is provided, including a memory array model having a plurality of memory array model locations, and a plurality of decoder models, each associated with a memory array model location. Each memory array model location includes a first data set accessed with the |
| 7567851 |
Method and system for dynamically changing the transport sequencing in a cluster tool |
July 28, 2009 |
| By dynamically adapting the transport sequencing rules of a cluster tool, the overall performance of the tool may be increased. In some illustrative embodiments, the transport sequencing rule for a robot handler may be dynamically changed when a lot of small size is present in one of |
| 7567135 |
Power monitoring device and methods thereof |
July 28, 2009 |
| To determine performance degradation at functional module in a normal power state due to a power control device, voltages are applied to oscillators at a power diagnostic module. A first voltage is a supply voltage for the data processing device, and a second voltage is a supply volt |
