| Patent Number |
Title Of Patent |
Date Issued |
| RE39518 |
Run to run control process for controlling critical dimensions |
March 13, 2007 |
| It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforw |
| RE35794 |
System for reducing delay for execution subsequent to correctly predicted branch instruction usi |
May 12, 1998 |
| A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate |
| 7475374 |
Clock grid driven by virtual leaf drivers |
January 6, 2009 |
| Various embodiments of methods and systems for providing virtual leaf driver nodes in a clock tree to drive a clock grid of an integrated circuit are disclosed. An integrated circuit may include a large number of clocked elements such as registers, flip-flops, etc. whose operation is |
| 7473623 |
Providing stress uniformity in a semiconductor device |
January 6, 2009 |
| A method includes forming a plurality of functional features on a semiconductor layer in a first region. A non-functional feature corresponding to the functional feature is formed adjacent at least one of the functional features disposed on a periphery of the region. A stress-inducin |
| 7473566 |
Method and apparatus for controlling a film formation process with multiple objectives |
January 6, 2009 |
| A method includes defining a plurality of objectives for a film formation process and employing a control equation incorporating the plurality of objectives to generate at least one operating recipe parameter for the film formation process. A system includes a film formation unit and a |
| 7472224 |
Reconfigurable processing node including first and second processor cores |
December 30, 2008 |
| In one embodiment, a processing node includes a first processor core and a second processor core. The first processor core includes a first cache memory, such as an L2 cache, for example. The second processor core includes a second cache memory, such as an L2 cache memory. The proces |
| 7468296 |
Thin film germanium diode with low reverse breakdown |
December 23, 2008 |
| In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provide |
| 7465956 |
Stacked organic memory devices and methods of operating and fabricating |
December 16, 2008 |
| The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more |
| 7465644 |
Isolation region bird's beak suppression |
December 16, 2008 |
| A structure for electrically isolating semiconductor devices includes a semiconducting layer and a layer of aluminum oxide formed in a pattern over the semiconducting layer, where the pattern exposes a portion of the semiconducting layer. The structure further includes an electrical |
| 7465639 |
Method for fabricating an SOI device |
December 16, 2008 |
| A method is provided for fabricating a silicon on insulator (SOI) device that includes a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer. The method comprises the steps of forming an MOS |
| 7465623 |
Methods for fabricating a semiconductor device on an SOI substrate |
December 16, 2008 |
| Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the |
| 7465408 |
Solutions for controlled, selective etching of copper |
December 16, 2008 |
| Disclosed are methods and systems of etching copper containing materials so that they have smooth and/or planar surface. In this connection, the systems and methods employ two different solutions to accomplish the etching. The first solution oxidizes the surface of the copper containing |
| 7464255 |
Using a shuffle unit to implement shift operations in a processor |
December 9, 2008 |
| A method and mechanism for performing shift operations using a shuffle unit. A processor includes a shuffle unit configured to perform shuffle operations responsive to shuffle instructions. The shuffle unit is adapted to support shift operations as well. In response to determining a |
| 7463939 |
Scheduling tools with queue time constraints |
December 9, 2008 |
| A method and apparatus for use in an automated manufacturing environment are disclosed. The method includes autonomously scheduling a consumer manufacturing domain entity for the consumption of services provided by a plurality of provider manufacturing domain entities in an automated |
| 7462563 |
Method of forming an etch indicator layer for reducing etch non-uniformities |
December 9, 2008 |
| By incorporating an etch control material after the formation of a material layer to be patterned, an appropriate material having a highly distinctive radiation wavelength may be used for generating a distinctive endpoint detection signal during an etch process. Advantageously, the m |
| 7462549 |
Shallow trench isolation process and structure with minimized strained silicon consumption |
December 9, 2008 |
| A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a co |
| 7462524 |
Methods for fabricating a stressed MOS device |
December 9, 2008 |
| Methods are provided for fabricating a stressed MOS device. One method comprises the steps of providing a substrate of a monocrystalline semiconductor material having a first lattice constant, and forming a conductive gate electrode overlying the substrate, the gate electrode having |
| 7461191 |
Segmented on-chip memory and requester arbitration |
December 2, 2008 |
| A memory access technique is provided that may be used in WLAN (Wireless Local Area Network) communication devices. An on-chip memory has multiple memory circuits forming individually addressable memory segments. An arbitration unit arbitrates between multiple requesters, each requesting |
| 7460968 |
Method and apparatus for selecting wafers for sampling |
December 2, 2008 |
| The present invention provides a method and apparatus for selecting wafers for sampling. The method includes determining a plurality of sampling rules associated with at least one of a plurality of wafers and selecting at least one wafer for sampling based on the plurality of sampling ru |
| 7460922 |
Scanner optimization for reduced across-chip performance variation through non-contact electrica |
December 2, 2008 |
| The disclosed embodiments reduce across-chip performance variation through non-contact electrical metrology. According to a feature is a process control system that includes a component that measures transistor electrical performance in a product wafer. Also included in the system is |
| 7460920 |
Determining scheduling priority using fabrication simulation |
December 2, 2008 |
| A method for processing workpieces in a process flow including a plurality of operations includes employing a fabrication simulation model of the process flow to determine an estimated completion time for a selected workpiece. The fabrication simulation model simulates the processing of |
| 7460369 |
Counterflow microchannel cooler for integrated circuits |
December 2, 2008 |
| A plurality of channels are formed in a base, e.g., a substrate of an integrated circuit, each channel extending between edges of the base. Two pairs of manifolds are provided, the first pair communicating with a first group of channels and the second pair communicating with a second |
| 7457374 |
DC offset cancellation for WLAN communication devices |
November 25, 2008 |
| A method of transmitting information in a WLAN (Wireless Local Area Network) network and corresponding WLAN communication devices and integrated circuit chips are provided. A correction signal is used for compensating for a dc offset in a data signal containing at least part of the i |
| 7456110 |
Method and apparatus for controlling etch selectivity |
November 25, 2008 |
| A method for controlling an etch process comprises providing a wafer having at least a first layer and a second layer formed over the first layer. The thickness of the second layer is measured. An etch selectivity parameter is determined based on the measured thickness of the second |
| 7456062 |
Method of forming a semiconductor device |
November 25, 2008 |
| A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subs |
| 7456058 |
Stressed MOS device and methods for its fabrication |
November 25, 2008 |
| Stressed MOS devices and methods for their fabrication are provided. The stressed MOS device comprises a T-shaped gate electrode formed of a material having a first Young's modulus. The T-shaped gate electrode includes a first vertical portion and a second horizontal portion. The ver |
| 7455450 |
Method and apparatus for temperature sensing in integrated circuits |
November 25, 2008 |
| A method and apparatus for temperature sensing in an IC. The IC includes a plurality of remote temperature sensors each coupled to a control logic unit. The plurality of remote temperature sensors may be distributed throughout the integrated circuit. The integrated circuit includes a |
| 7451411 |
Integrated circuit design system |
November 11, 2008 |
| The present invention provides an integrated circuit design system, comprising providing a design system in a computer system, providing a layout design tool coupled to the design system, wherein the layout design tool creates an interconnect structure to satisfy electromigration cri |
| 7451337 |
Guaranteed edge synchronization for multiple clocks |
November 11, 2008 |
| A method and apparatus for guaranteeing clock edge synchronization is disclosed. In one embodiment, a system for synchronizing clock signals includes a clock unit and a synchronization unit. Both the clock unit and the synchronization unit may be configured to receive a reference clock |
| 7451324 |
Secure execution mode exceptions |
November 11, 2008 |
| A method and system for handling a security exception. The method includes creating a security exception stack frame in secure memory at a base address. The method also includes writing a faulting code sequence address and one or more register values into the security exception stack |
| 7449413 |
Method for effectively removing polysilicon nodule defects |
November 11, 2008 |
| According to one exemplary embodiment, a method includes a step of forming a polysilicon layer over a substrate by using a deposition process, where the deposition process causes polysilicon nodule defects to form on a top surface of the polysilicon layer. The method further includes per |
| 7449348 |
Feedback control of imprint mask feature profile using scatterometry and spacer etchback |
November 11, 2008 |
| The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilit |
| 7446036 |
Gap free anchored conductor and dielectric structure and method for fabrication thereof |
November 4, 2008 |
| A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor laye |
| 7445945 |
Method and apparatus for dynamic adjustment of a sampling plan based on wafer electrical test da |
November 4, 2008 |
| The present invention provides a method and apparatus for dynamic adjustment of a sampling plan. The method includes accessing wafer electrical test data associated with at least one workpiece that has been processed by at least one processing tool. The method also includes determini |
| 7444200 |
Preventative maintenance scheduling incorporating facility and loop optimization |
October 28, 2008 |
| A method for scheduling preventative maintenance tasks includes defining a set of global time periods. Members of a set of preventative maintenance tasks associated with a plurality of machines for are scheduled execution during the global time periods based on capacities of the machines |
| 7442971 |
Self-biasing transistor structure and an SRAM cell having less than six transistors |
October 28, 2008 |
| By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows |
| 7442638 |
Method for forming a tungsten interconnect structure with enhanced sidewall coverage of the barr |
October 28, 2008 |
| By performing a re-sputter process during the formation of a barrier layer for a contact opening in a tungsten-based process, the reliability of the tungsten deposition, as well as the performance of the resulting contact plug, may be enhanced. During the re-sputtering process, a thickne |
| 7442601 |
Stress enhanced CMOS circuits and methods for their fabrication |
October 28, 2008 |
| A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated |
| 7441446 |
Method and apparatus for determining surface characteristics by using SPM techniques with acoust |
October 28, 2008 |
| By digitizing the UFM signal without using a lock-in amplifier, substantially all of the information initially contained in the UFM output signal may be maintained and may then be used for further data processing. Consequently, any type of model or evaluation algorithm may be used wi |
| 7441136 |
System for predictive processor component suspension and method thereof |
October 21, 2008 |
| An instruction cycle is determined from instructions stored in a cache, where the instruction cycle represents the sequence of instructions predicted to be executed by the processing device that are resident in the cache. The duration of the instruction cycle is estimated and one or |
| 7440392 |
Wireless receiver deinterleaver having partitioned memory |
October 21, 2008 |
| A deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with a prescribed subcarrier frequency. Each code word fragment includes a prescribed number |
| 7439127 |
Method for fabricating a semiconductor component including a high capacitance per unit area capa |
October 21, 2008 |
| A method is provided for fabricating a semiconductor component that includes a capacitor having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semic |
| 7439120 |
Method for fabricating stress enhanced MOS circuits |
October 21, 2008 |
| A stress enhanced MOS circuit and methods for its fabrication are provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls |
| 7433224 |
System and method for forcing an SRAM into a known state during power-up |
October 7, 2008 |
| There is disclosed a static random access memory (SRAM) device that stores an embedded program that is accessible when the SRAM device is powered up. The SRAM device comprises a plurality of storage cells, each of the storage cells comprises a data latch having an input and an output, |
| 7432558 |
Formation of semiconductor devices to achieve <100> channel orientation |
October 7, 2008 |
| A semiconductor device may include a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer. The fin may include a side surface and a top surface, and the side surface may have a <100> orientation. A first gate may be formed on the |
| 7432557 |
FinFET device with multiple channels |
October 7, 2008 |
| A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels |
| 7432178 |
Bit line implant |
October 7, 2008 |
| A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of |
| 7432174 |
Methods for fabricating semiconductor substrates with silicon regions having differential crysta |
October 7, 2008 |
| A method is provided for fabricating a differential semiconductor substrate. A first structure is provided which comprises a first semiconductor substrate including a first semiconductor region, and a first oxide layer overlying a surface of the first semiconductor substrate. The fir |
| 7432136 |
Transistors with controllable threshold voltages, and various methods of making and operating sa |
October 7, 2008 |
| In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, the active layer being doped with a first type of dopant material, the bulk substrate having an inner well formed therein adjacent |
| 7430622 |
Extended fairness arbitration for chains of point-to -point devices having multiple virtual chan |
September 30, 2008 |
| Buffer-level arbitration is used to allocate released buffers, based on received flow control credits, between local packets and received packets on respective virtual channels in accordance with a determined insertion rate relative to a second number of received packets to be forwarded. |
