| Patent Number |
Title Of Patent |
Date Issued |
| 5153841 |
Method of and apparatus for semi-conductor wafer selection |
October 6, 1992 |
| A method and apparatus for lifting select semi-conductor wafers from a quartz wafer boat. A removable transfer platform is provided for receiving a quartz wafer boat and positioning the wafer boat above upwardly extending fingers adapted for engaging wafers disposed therein. The upwa |
| 5084404 |
Gate array structure and process to allow optioning at second metal mask only |
January 28, 1992 |
| A structure and method for forming a semicustom integrated circuit in which customization can be performed using only a single masking step. Vias in an insulation layer between first and second metal are made larger than first metal lines so that after deposition of second metal, a final |
| 5068830 |
High speed static RAM sensing system |
November 26, 1991 |
| A current differential sense amplifier for static RAM cells which couple one of a pair of bit lines to a current source for a high speed read operation. The sense amplifier has current mirrors which amplify the current on each of the bit lines. The amplified currents are fed into an |
| 4994891 |
Shielded transistor device |
February 19, 1991 |
| The invention comprises an operational amplifier circuit having a shielded transistor device whose drain is surrounded by a gate comprising an annular ribbon of polysilicon. The gate is connected to a trackable potential that fluctuates but is keyed to a voltage slightly above the av |
| 4954455 |
Semiconductor memory device having protection against alpha strike induced errors |
September 4, 1990 |
| The invention comprises an improved bipolar memory device having enhanced protection against the effects of alpha particles comprising at least one memory cell having a buried layer forming at least a portion of the collector of one of the transistors in the memory cell, said buried laye |
| 4943942 |
Full-duplex modem using a single processor |
July 24, 1990 |
| Method of scheduling execution of transmit-side and receive-side procedures by a single processor in a full-duplex modem. Buffers of minimal size are employed in conjunction with the processor to guarantee no errors in the signal processing procedures. In one embodiment, transmit-side pr |
| 4910701 |
Split array binary multiplication |
March 20, 1990 |
| A system for binary multiplication based upon the modified Booth algorithm incorporating a Booth multiplex decoder, partial modified Booth arrays and partial product reduction adders. The system is comprised of Booth multiplexer cells, Booth multiplexer and adder cells, sign extension |
| 4890260 |
Content addressable memory array with maskable and resettable bits |
December 26, 1989 |
| A content addressable memory array includes an array of M words containing bits configured in N bits for each word. One of the bits in each of the words is a settable skip bit, and during a search of the memory array, the array is examined to detect the presence therein of skip bits. If |
| 4847812 |
FIFO memory device including circuit for generating flag signals |
July 11, 1989 |
| A FIFO memory device facilitates transfer of data between a host CPU and a peripheral device in one of a number of modes. In one mode the FIFO memory device functions as two FIFO memories, one for passing data from the host CPU to the peripheral device, and one for passing data to the ho |
| 4839842 |
Digital tone detection and generation |
June 13, 1989 |
| Fast methods of tone detection and tone generation disclosed are particularly suitable for implementation in a digital signal processor. Chebyshev polynomials are employed to generate periodic waveforms and to detect such waveforms. In an alternative aspect of the invention, trigonom |
