| Patent Number |
Title Of Patent |
Date Issued |
| 6004861 |
Process for making a discontinuous source/drain formation for a high density integrated circuit |
December 21, 1999 |
| A semiconductor process including forming a gate dielectric on a semiconductor substrate. First and second conductive gates are then formed on the gate dielectric. The conductive gates are aligned over respective channel regions of the substrate. The channel regions are laterally dis |
| 5998270 |
Formation of oxynitride and polysilicon layers in a single reaction chamber |
December 7, 1999 |
| A semiconductor device fabrication process in which an oxynitride layer and a polysilicon layer are formed in the same reaction chamber is provided. In accordance with one embodiment of the invention, a semiconductor device is formed by forming, in a reaction chamber, an oxynitride layer |
| 5995030 |
Apparatus and method for a combination D/A converter and FIR filter employing active current div |
November 30, 1999 |
| An active current steering semi-digital FIR filter for a digital-to-analog conversion circuit, which includes a shift register having a 1-bit digital input stream and a plurality of output taps, where each output tap provides a 1-bit signal which has a value of a logic 1 or a logic 0, an |
| 5994738 |
Silicon oxide insulator (SOI) semiconductor having selectively linked body |
November 30, 1999 |
| A silicon oxide insulator (SOI) device includes an SOI layer supported on a silicon substrate. A body region is disposed on the SOI layer, and the body region is characterized by a first conductivity type. Source and drain regions are juxtaposed with the body region, with the source and |
| 5990532 |
Semiconductor arrangement with lightly doped regions under a gate structure |
November 23, 1999 |
| The formation of lightly doped regions under a gate of a transistor via gate autodoping is disclosed. One embodiment of the invention is a method having four steps. In the first step, a gate having two sidewalls is provided over a gate oxide over a semiconductor substrate; source and |
| 5989957 |
Process for fabricating semiconductor memory device with high data retention including silicon o |
November 23, 1999 |
| A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon oxynitride etch stop layer which is formed using Plasma |
| 5986283 |
Test structure for determining how lithographic patterning of a gate conductor affects transisto |
November 16, 1999 |
| The present invention advantageously provides a test structure and method for determining how lithographic patterning of transistor gate conductors laterally spaced from conductors affects the operation of transistors which employ the gate conductors. The test structure includes a sequen |
| 5982784 |
Bandwidth sharing for remote and local data transfers using multicarrier modulation over common |
November 9, 1999 |
| A system and method for allowing concurrent local and remote network data transfers on a common data transmission link using frequency bandwidth partitioning and reservation is provided. Multiple frequency bandwidth segments are configured for remote data transmissions between the local |
| 5981368 |
Enhanced shallow junction design by polysilicon line width reduction using oxidation with integr |
November 9, 1999 |
| A method of forming a transistor includes forming a gate dielectric layer upon a substrate, forming a polysilicon layer upon the gate dielectric layer and then forming a thin nitride layer upon the gate polysilicon layer. The thin nitride layer is then pattern etched to define a nitride |
| 5981358 |
Encroachless LOCOS isolation |
November 9, 1999 |
| The present invention provides a fabrication process for fabricating an integrated circuit substrate structure having LOCOS isolation areas formed such that oxidation encroachment at an active surface region patterned on the substrate is less than 0.1 .mu.m. The fabrication process inclu |
| 5981341 |
Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned fl |
November 9, 1999 |
| A method for making a self-aligned isolated flash memory core without damaging tunnel oxide layers between memory element stacks and the silicon substrate supporting the stacks includes depositing three sidewall layers on the stacks, prior to etching isolation trenches between the stacks |
| 5977602 |
Semiconductor device having an oxygen-rich punchthrough region extending through the length of t |
November 2, 1999 |
| A semiconductor device having an oxygen-rich punchthrough region under the channel region, and a process for fabricating such a device are disclosed. In accordance with one embodiment, a semiconductor device is formed by forming an oxygen-rich punchthrough region in a substrate, and form |
| 5976948 |
Process for forming an isolation region with trench cap |
November 2, 1999 |
| A method for producing a semiconductor device using an improved trench isolation technique includes, first, forming a masking layer over a device layer. A first portion of the masking layer and an underlying portion of the device layer are removed to form at least one trench. A second po |
| 5976925 |
Process of fabricating a semiconductor devise having asymmetrically-doped active region and gate |
November 2, 1999 |
| A semiconductor device having asymmetrically-doped gate electrode and active region and a process of fabricating such a device is provided. According to one embodiment of the invention, a polysilicon layer is formed over the substrate. The polysilicon layer is then implanted with a f |
| 5972727 |
Reticle sorter |
October 26, 1999 |
| A reticle sorter and a semiconductor fabrication facility employing one or more reticle sorters is provided. The reticle sorter(s) generally lies between a reticle storage system and a group of one or more photolithography exposure tools (e.g., steppers) and is configured for sorting |
| 5970383 |
Method of manufacturing a semiconductor device with improved control of deposition layer thickne |
October 19, 1999 |
| The uniformity of the thickness of a deposition layer, generated by a chemical vapor deposition (CVD) process, on a semiconductor wafer is enhanced by providing an undercoating on the deposition chamber. The undercoating is formed at a deposition rate significantly faster than the de |
| 5970370 |
Manufacturing capping layer for the fabrication of cobalt salicide structures |
October 19, 1999 |
| An improved process for manufacturing cobalt silicide layers uses two capping layers. A first capping layer of titanium nitride prevents the formation of a cobalt/titanium intermetallic. A subsequently formed titanium metallic layer getters impurities from outgassing and the ambient |
| 5970350 |
Semiconductor device having a thin gate oxide and method of manufacture thereof |
October 19, 1999 |
| A process for fabricating a device having a thin gate oxide layer on which a gate electrode is formed is disclosed. The thin gate oxide layer is formed using an ion implantation process in order to reliably control the thickness of the gate oxide layer. A nitrogen-containing species is u |
| 5970349 |
Semiconductor device having one or more asymmetric background dopant regions and method of manuf |
October 19, 1999 |
| Semiconductor devices having one or more asymmetric background dopant regions and methods of fabrication thereof are provided. The asymmetric background dopant regions may be formed using a patterned mask with wider openings than conventional masks while substantially maintaining device |
| 5970311 |
Method and structure for optimizing the performance of a semiconductor device having dense trans |
October 19, 1999 |
| A method and structure for optimizing the performance of a semiconductor device having dense transistors. A method consistent with the present invention includes forming a first test structure on a first substrate portion. The first test structure includes a transistor having a gate |
| 5964883 |
Arrangement and method for handling bus clock speed variations |
October 12, 1999 |
| An arrangement for monitoring clock frequency variations on a peripheral bus is provided to improve operations of the peripheral device despite changes in the clock frequency. In one aspect of the arrangement, a processing unit is coupled to a host bus which in turn is coupled to a p |
| 5964881 |
System and method to control microprocessor startup to reduce power supply bulk capacitance need |
October 12, 1999 |
| A system for controlling a clock rate of a microprocessor which includes a core clock operatively coupled to the processor, the core clock providing the microprocessor with a core clock signal for clocking the processor. A power supply operatively coupled to the microprocessor provides p |
| 5963810 |
Semiconductor device having nitrogen enhanced high permittivity gate insulating layer and fabric |
October 5, 1999 |
| A semiconductor device having a nitrogen enhanced high permittivity gate insulating layer and a process for manufacturing such a device is provided. Consistent with one embodiment, a high permittivity gate insulating layer is formed over a substrate using a nitrogen bearing gas. The |
| 5963159 |
Arrangement and method for controlling gain of analog-to-digital converters |
October 5, 1999 |
| A gain control arrangement for use in analog-to-digital conversion includes a current generator that generates gain currents as a function of externally applied resistances. The gain currents are sequentially provided to the analog-to-digital converter, enabling the converter to use |
| 5952696 |
Complementary metal oxide semiconductor device with selective doping |
September 14, 1999 |
| A semiconductor device and fabrication thereof is disclosed in which devices are formed on two devices regions of opposite conductivity types by selectively masking and implanting the same type of dopant into active regions of both device regions. The process includes masking part of the |
| 5946581 |
Method of manufacturing a semiconductor device by doping an active region after formation of a r |
August 31, 1999 |
| In a semiconductor device fabrication process, an active region of the semiconductor device is formed by doping an active region after formation of a relatively thick oxide layer. According to the process, a gate electrode is formed on a substrate and a relatively thick oxide layer is |
| 5946214 |
Computer implemented method for estimating fabrication yield for semiconductor integrated circui |
August 31, 1999 |
| A computer is used to estimate a fabrication yield for a semiconductor product under design which includes a plurality of integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme in the form of redundant rows and/or columns. A bitmap fai |
| 5945352 |
Method for fabrication of shallow isolation trenches with sloped wall profiles |
August 31, 1999 |
| The present invention provides a method for fabricating shallow isolation trenches with sloped walls in semiconductor wafers. The method uses a conformal polysilicon layer to form an etch barrier over trench regions in a semiconductor substrate. This etch barrier has areas of varying |
| 5943596 |
Fabrication of a gate electrode stack using a patterned oxide layer |
August 24, 1999 |
| A semiconductor device having a gate electrode stack formed using a patterned oxide layer is disclosed. The device is formed by forming an oxide layer over a surface of a substrate and forming at least one opening in the oxide layer. A high permittivity plug (e.g., a BST plug) is formed |
| 5940718 |
Nitridation assisted polysilicon sidewall protection in self-aligned shallow trench isolation |
August 17, 1999 |
| A method for fabricating a semiconductor device including a silicon substrate and plural silicon stacks thereon includes forming a nitride shield layer on the substrate and stacks to cover the stacks, such that the stacks are protected from loss of critical dimension during subsequent |
| 5940698 |
Method of making a semiconductor device having high performance gate electrode structure |
August 17, 1999 |
| A semiconductor device having a high performance gate electrode structure and a process of fabricating such a device. A semiconductor device in accordance with an embodiment of the invention is formed by forming a gate insulating layer is over a substrate. A diffusion barrier layer is fo |
| 5939750 |
Use of implanted ions to reduce oxide-nitride-oxide (ONO) etch residue and polystringers |
August 17, 1999 |
| A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. The method including forming a first polysilicon (poly I) layer on an oxide coated substrate and masking the poly I layer to pattern the first memory cell and the second memory |
| 5937303 |
High dielectric constant gate dielectric integrated with nitrogenated gate electrode |
August 10, 1999 |
| A semiconductor process for forming a gate electrode of an MOS transistor. A gate dielectric is deposited on an upper surface of a semiconductor substrate. A dielectric constant of the gate dielectric layer is in the range of approximately 25 to 300. A thickness of the gate dielectric is |
| 5937301 |
Method of making a semiconductor device having sidewall spacers with improved profiles |
August 10, 1999 |
| A semiconductor device having improved spacers and a process for fabricating the same is provided. The semiconductor device is formed by forming at least one gate electrode over a substrate and forming a spacer layer over the gate electrode. A nitrogen bearing species is implanted in |
| 5930632 |
Process of fabricating a semiconductor device having cobalt niobate gate electrode structure |
July 27, 1999 |
| A semiconductor device having a cobalt niobate-cobalt silicide gate electrode structure is provided. A semiconductor device, consistent with one embodiment of the invention, is formed by forming a cobalt niobate gate insulating layer over the substrate and forming a cobalt silicide l |
| 5930340 |
Device and method for isolating voice and data signals on a common carrier |
July 27, 1999 |
| A device and system for isolating voice and data signals transmitted on an internal telephone wire network is disclosed. The device further includes voice and/or data connectors coupled to the network. One or more filters are coupled between the network and the voice and data connectors |
| 5925914 |
Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance |
July 20, 1999 |
| A method of making a transistor is also disclosed, including the steps of forming a gate oxide layer (106) over a semiconductor substrate (100) and forming a gate structure (108) over a portion of the gate oxide layer (106), thereby separating the transistor into a first region (114) and |
| 5923993 |
Method for fabricating dishing free shallow isolation trenches |
July 13, 1999 |
| A fabrication process for manufacturing integrated circuits with isolation trenches. The process includes the use of two nitride layers and an oxide layer formed by high density plasma oxidation, to provide isolation trenches free of dishing. The isolated regions are useable for fabricat |
| 5923949 |
Semiconductor device having fluorine bearing sidewall spacers and method of manufacture thereof |
July 13, 1999 |
| Fluorine bearing spacers on the sidewalls of gate electrodes of a semiconductor device are provided to suppress hot carrier injection in the semiconductor device. In accordance with one embodiment of the invention, a semiconductor device is formed by forming at least one gate electrode o |
| 5920786 |
Method for fabricating shallow isolation trenches using angular photoresist profiles to create s |
July 6, 1999 |
| The present invention provides a method of constructing trenches for use in microelectronic circuit structures. A photolithographic method is used to create trenches with sloped walls shaping the photoresist masks into sloped profiles. These photoresist masks effectively shape the underl |
| 5918133 |
Semiconductor device having dual gate dielectric thickness along the channel and fabrication the |
June 29, 1999 |
| Generally, the present invention relates to a semiconductor device having a dual thickness gate dielectric along the channel and a process of fabricating such a device. By providing a dual thickness gate dielectric, the gate dielectric can, for example, be optimized to the transistor and |
| 5914873 |
Distributed voltage converter apparatus and method for high power microprocessor with array conn |
June 22, 1999 |
| The present invention provides a relief to the low voltage, high current spiral trend being seen in the microprocessor industry. A microprocessor module is designed to receive a voltage V2, which is substantially higher than a logic gate utilization voltage V3. V2 is supplied at a curren |
| 5913116 |
Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidew |
June 15, 1999 |
| In semiconductor device fabrication process, an active region of a semiconductor device is formed by diffusing a dopant out of a sidewall spacer. In the fabrication process, a gate electrode having a sidewall adjacent an active region is formed on a substrate and a doped spacer layer |
| 5901090 |
Method for erasing flash electrically erasable programmable read-only memory (EEPROM) |
May 4, 1999 |
| A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, and a power source for supplying a plurality of voltages to the cells. A controller controls the |
| 5898342 |
Power amplifier arrangement and method for data signal interface |
April 27, 1999 |
| An arrangement and method using power more efficiently for signal amplification. The approach is particularly advantageous in application environments where digital information is converted to the analog domain and carried at a variety of different magnitudes. One embodiment involves |
| 5897358 |
Semiconductor device having fluorine-enhanced transistor with elevated active regions and fabric |
April 27, 1999 |
| A semiconductor device having a fluorine-enhanced transistor with elevated active regions and process for fabricating such a device is provided. A semiconductor device, consistent with one embodiment of the invention, includes a substrate and at least one pair of elevated active regions |
| 5893744 |
Method of forming a zero layer mark for alignment in integrated circuit manufacturing process em |
April 13, 1999 |
| A method of forming an alignment mark in a wafer during the manufacture of shallow isolation trenches for semiconductor devices provides a nitride layer on a substrate prior to the formation of the alignment mark. Once the nitride layer has been formed, etching is performed to create the |
| 5890269 |
Semiconductor wafer, handling apparatus, and method |
April 6, 1999 |
| A semiconductor wafer comprising a single crystalline lattice suitable for use in the manufacture of integrated circuits, namely computer chips and dies, wherein a diameter of the wafer is greater than approximately 150 millimeters and wherein the wafer includes a first hole extending th |
| 5889697 |
Memory cell for storing at least three logic states |
March 30, 1999 |
| A memory cell for storing data having at least three logic states includes a pair of storage devices and third-level storage and refresh circuitry coupled to a pair of storage nodes. The storage devices maintain multi-level signals representative of first and second logic states at the |
| 5886899 |
Method for analyzing the performance of a microprocessor |
March 23, 1999 |
| A method for analyzing the performance of a logic circuit driven by a clock signal, such as a microprocessor, identifies a number of operations of interest in a logic circuit and represents the presence of each of such operations by a different symbol. One or more of these symbols are ou |
