| Patent Number |
Title Of Patent |
Date Issued |
| 6313019 |
Y-gate formation using damascene processing |
November 6, 2001 |
| A method for fabricating a Y-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the fi |
| 6309926 |
Thin resist with nitride hard mask for gate etch application |
October 30, 2001 |
| A method of forming a gate structure is provided. In the method, a nitride layer is formed on a gate material layer. An ultra-thin photoresist layer is formed on the nitride layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for the |
| 6307784 |
Negative gate erase |
October 23, 2001 |
| A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for |
| 6306769 |
Use of dual patterning masks for printing holes of small dimensions |
October 23, 2001 |
| The present invention addresses a problem associated with exposing a photoresist layer of non-uniform thickness. Oftentimes, trench patterns etched into a layer of a semiconductor structure will have trenches of varying sizes. Larger trenches in the structure become filled with photo |
| 6304836 |
Worst case design parameter extraction for logic technologies |
October 16, 2001 |
| The present invention provides for more realistic worst case extreme determinations for an integrated circuit as compared to conventional techniques. In particular, the present invention provides a framework which affords for improved linkage between semiconductor manufacturing proce |
| 6300148 |
Semiconductor structure with a backside protective layer and backside probes and a method for co |
October 9, 2001 |
| A semiconductor structure with a backside protective layer and backside probes and a method for constructing the structure. Consistent with one embodiment of the invention, the semiconductor structure comprises a substrate having a first surface, on which a circuit interconnect layer is |
| 6297111 |
Self-aligned channel transistor and method for making same |
October 2, 2001 |
| A method for forming a transistor comprises the steps of: forming a gate stack on the surface of a semiconductor substrate; implanting a first dose of an impurity into the substrate at a sufficient energy to penetrate at least a portion of the gate stack to provide a portion of the impur |
| 6294412 |
Silicon based lateral tunneling memory cell |
September 25, 2001 |
| An SRAM memory cell device is provide having a single transistor and a single RTD latch structure. The single transistor and RTD latch structure are formed on a very thin silicon layer, typically in the range of 250 to 300 .ANG. thick, allowing for increased memory cell density over a gi |
| 6288951 |
Method and apparatus for continuously regulating a charge pump output voltage using a capacitor |
September 11, 2001 |
| A non-volatile memory and method for continuously regulating an output of a charge pump of the non-volatile memory for long periods of time at a target output voltage. |
| 6287877 |
Electrically quantifying transistor spacer width |
September 11, 2001 |
| A method for electrically quantifying a semiconductor device's spacers' width. In one embodiment, a method comprises the step of measuring a resistance across a region of interest of each of a plurality of semiconductor structures including the semiconductor device in question, where |
| 6275927 |
Compressing variable-length instruction prefix bytes |
August 14, 2001 |
| A microprocessor configured to reduce variance in the length of variable length instructions by compressing multiple prefix bytes into a single byte is disclosed. The microprocessor is configured with a predecode unit and an instruction cache. The predecode unit is configured to receive |
| 6255124 |
Test arrangement and method for thinned flip chip IC |
July 3, 2001 |
| According to one aspect of the disclosure, the present invention provides methods and arrangements for testing a flip chip semiconductor device after the back side of the chip has been thinned to expose a selected region in the substrate. For some chips, thinning removes substrate ma |
| 6253621 |
Micro-void detection |
July 3, 2001 |
| According to an example embodiment of the present invention, a semiconductor device having conductive structure is analyzed using acoustic energy. Acoustic energy is generated in the device, and a resulting acoustic wave is detected. Using the detected wave, an index of refraction of |
| 6248628 |
Method of fabricating an ONO dielectric by nitridation for MNOS memory cells |
June 19, 2001 |
| A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes providing a semiconductor substrate and thermally growing a first silicon oxide layer overlying the semiconductor substrate. A thermal anneal is performed after growing the first silicon oxide la |
| 6248603 |
Method of measuring dielectric layer thickness using SIMS |
June 19, 2001 |
| Semiconductor structures having dielectric material layers that are below 3 nanometers in thickness can now be measured with greater precision and in less time using a SIMS device. In an example embodiment of the present invention, a method of measuring the thickness of a dielectric mate |
| 6248600 |
Led in substrate with back side monitoring |
June 19, 2001 |
| Post-manufacturing analysis of a semiconductor device is enhanced via a method that uses a light emitting diode (LED) formed in a semiconductor die. According to an example embodiment of the present invention, a LED is formed within a semiconductor die having a circuit side opposite a ba |
| 6246096 |
Totally self-aligned transistor with tungsten gate |
June 12, 2001 |
| A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. A mid-gap electrode is also self-aligned to the transistor. The electrode is |
| 6245638 |
Trench and gate dielectric formation for semiconductor devices |
June 12, 2001 |
| Semiconductor device fabrication techniques which integrate the formation of trench isolation areas and gate insulating layers are provided. The fabrication techniques include forming one or more sacrificial layers, such as nitrided oxide layers, over regions of the substrate adjacent to |
| 6245584 |
Method for detecting adjustment error in photolithographic stepping printer |
June 12, 2001 |
| An adjustment error in a photolithographic stepping printer is detected by applying photoresist to a semiconductor wafer, and exposing the wafer to substantially identical light images in multiple locations using a stepping printer. The light images are defined by an optical reticle and |
| 6242924 |
Method for electronically measuring size of internal void in electrically conductive lead |
June 5, 2001 |
| The size of an internal void in an electrically conductive lead is measured by determining its electrical resistance at a plurality of A.C. frequencies, ranging from D.C. to a frequency on the order of 50 to 100 GHz at which the majority of current flows along the skin of the lead. The |
| 6242306 |
Dual bit isolation scheme for flash memory devices having polysilicon floating gates |
June 5, 2001 |
| The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is prov |
| 6240020 |
Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory |
May 29, 2001 |
| A flash memory device includes an array of core cell blocks and page buffers with supporting input/output circuitry. The flash memory device, in addition, contains a method for shielding the bitline for a precharging scheme in which the bitline line of each page buffer is charged prior t |
| 6238982 |
Multiple threshold voltage semiconductor device fabrication technology |
May 29, 2001 |
| An integrated circuit process technology for simultaneously forming multiple threshold voltage devices is disclosed. Devices having both high speed and low power consumption can be fabricated for use in integrated circuits having a need for both, such as microprocessors having cache |
| 6238830 |
Active control of temperature in scanning probe lithography and maskless lithograpy |
May 29, 2001 |
| A system for monitoring and regulating a photoresist temperature in a maskless lithography pattern transfer process is disclosed. The system includes a photoresist layer overlying a substrate and a material associated with the photoresist layer, wherein the material exhibits a transf |
| 6232048 |
Method for preparing narrow photoresist lines |
May 15, 2001 |
| A method of preparing a narrow photoresist line by first forming a resist pattern on a substrate, wherein a resist line is designed to have a width "w" in excess of a desired width "w.sup.1 " The resist is then subjected to ionic bombardment with ionized particles in a direction normal t |
| 6217936 |
Semiconductor fabrication extended particle collection cup |
April 17, 2001 |
| An improved particle-collecting cup using a fabrication protective device for use in processing semiconductor wafers includes a deflective surface, a protective shield and a protective lip to protect the surface of the semiconductor. The deflective surface encircles the semiconductor and |
| 6215896 |
System for enabling the real-time detection of focus-related defects |
April 10, 2001 |
| A real-time hotspot detection system is disclosed. In a preferred embodiment, the real-time hotspot detection system of the present invention comprises a photolithography stepper that has been modified to output z-height focus data for each cell to a fault detection module of the pre |
| 6211044 |
Process for fabricating a semiconductor device component using a selective silicidation reaction |
April 3, 2001 |
| A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques followed by a selective silicidation reaction process to reduce the lateral dimension of the hard-mask. The silicidation reaction is carried out by selectively reactin |
| 6211000 |
Method of making high performance mosfets having high conductivity gate conductors |
April 3, 2001 |
| A method of fabricating an integrated circuit includes forming a gate stack upon an active region of a substrate which includes a gate dielectric, a polysilicon gate conductor and a polysilicon consumption metal layer portion. The polysilicon consumption metal layer portion is then react |
| 6207485 |
Integration of high K spacers for dual gate oxide channel fabrication technique |
March 27, 2001 |
| A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so |
| 6205860 |
Apparatus and method for determining a differential pressure with respect to a remote site |
March 27, 2001 |
| A method of measuring the differential pressure of two fluid pressure sources includes connecting a manometer having a wireless transceiver for transmitting measured pressures to a remote location and connecting a second manometer to a second pressures source. The second manometer then |
| 6205059 |
Method for erasing flash electrically erasable programmable read-only memory (EEPROM) |
March 20, 2001 |
| A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells, a power supply, and a controller which cooperates with the power supply to apply an erase pulse to the cells, and then erase verify a first byte of cells |
| 6205057 |
System and method for detecting flash memory threshold voltages |
March 20, 2001 |
| A memory array includes a first flash memory cell, a second flash memory cell having a programmed threshold voltage, a first current sink, a second current sink, and a control circuit. The first flash memory cell is electrically interconnected with the first current sink and the cont |
| 6196734 |
CD uniformity by active control of developer temperature |
March 6, 2001 |
| A system for regulating temperature of a developer is provided. The system includes a plurality of optical fibers, each optical fiber directing radiation to respective portions of the developer. Radiation reflected from the respective portions are collected by a measuring system which |
| 6191034 |
Forming minimal size spaces in integrated circuit conductive lines |
February 20, 2001 |
| A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to |
| 6191012 |
Method for forming a shallow junction in a semiconductor device using antimony dimer |
February 20, 2001 |
| A method for forming a shallow junction in a semiconductor device includes the steps of ion implanting a molecular antimony dimer (Sb.sub.2 +) into a semiconductor substrate. The antimony dimer implantation process creates a shallow doped junction having a high dopant concentration and a |
| 6190980 |
Method of tilted implant for pocket, halo and source/drain extension in ULSI dense structures |
February 20, 2001 |
| A method of performing tilted implantation for pocket, halo and source/drain extensions in ULSI dense structures. The method overcomes the process limit, due to shadowing effects, in dense structures, of using large angle tilted implant techniques in ULSI circuits. A gate opening in |
| 6188110 |
Integration of isolation with epitaxial growth regions for enhanced device formation |
February 13, 2001 |
| A method of forming integrated isolation regions and active regions includes first forming a plurality of dielectric layers upon a semiconductor substrate. Then, a patterned mask is applied to define portions of the dielectric layers that will remain to form isolation regions and to |
| 6184105 |
Method for post transistor isolation |
February 6, 2001 |
| A method of fabricating integrated circuit including field effect transistors (FET) having source and drain regions and a gate and with LOCOS isolation by selectively forming, after the FETs are fabricated, trench openings in the source or drain regions or in the LOCOS isolation to m |
| 6180465 |
Method of making high performance MOSFET with channel scaling mask feature |
January 30, 2001 |
| A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A dielectric layer is then formed on the surface of the substrate, portions of which are then etched to |
| 6177989 |
Laser induced current for semiconductor defect detection |
January 23, 2001 |
| A process and apparatus for analyzing an integrated circuit using laser induced current and photoemissions. A laser source is positioned to scan the integrated circuit with laser light and induce current in nodes of the circuit. Laser light reflected from the integrated circuit is filter |
| 6177687 |
Semiconductor device having gate electrode shared between two sets of active regions and fabrica |
January 23, 2001 |
| Semiconductor devices having a gate electrode shared by two sets of active regions and methods of manufacture thereof are provided. In one embodiment, a first substrate is provided and a gate electrode is disposed over the first substrate. A second substrate is disposed over the gate |
| 6172402 |
Integrated circuit having transistors that include insulative punchthrough regions and method of |
January 9, 2001 |
| An integrated circuit includes a plurality of transistors formed to include insulative punchthrough regions. Each of the plurality of transistors includes a channel formed upon a substrate, an insulative punchthrough region formed below the channel, a source formed upon the insulative |
| 6171174 |
System and method for controlling a multi-arm polishing tool |
January 9, 2001 |
| A system and method for controlling a polishing tool having multiple arms is provided. In accordance with one embodiment, a first removal rate for each arm based on a first wafer run is determined. A downforce adjustment input for each arm is then determined based on a process model, for |
| 6165858 |
Enhanced silicidation formation for high speed MOS device by junction grading with dual implant |
December 26, 2000 |
| A method of making a MOS transistors in an integrated circuit includes forming a plurality of doped source and drain regions adjacent respective gate structures that include gate dielectrics, gate conductors and spacers. The plurality of doped source and drain regions are formed at d |
| 6162718 |
High speed bump plating/forming |
December 19, 2000 |
| A plurality of uniform bumps are formed on a semiconductor device by forming a plurality of bond limiting metallization areas. The surface of the semiconductor device is then plated with a plating metal that will be alloyed with the solder of the solder bump, said solder and the plating |
| 6162587 |
Thin resist with transition metal hard mask for via etch application |
December 19, 2000 |
| A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transi |
| 6157572 |
Method for erasing flash electrically erasable programmable read-only memory (EEPROM) |
December 5, 2000 |
| A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power supply for generating erase pulses. A controller controls the power supply to apply an erase |
| 6153455 |
Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer |
November 28, 2000 |
| A method of developing a transistor, such as a complimentary MOS (CMOS) transistor, that includes lightly doped drain (LDD) regions which uses disposable spacers, and includes the step of adding an oxide spacer etch after a disposable nitride spacer removal and between source/drain impla |
| 6151119 |
Apparatus and method for determining depth profile characteristics of a dopant material in a sem |
November 21, 2000 |
| An apparatus and method for the determination of a depth profile and/or one or more depth profile characteristics of a dopant material in a semiconductor device includes a light source which can illuminate the device at two or more illumination wavelengths, a detector that receives s |
