| Patent Number |
Title Of Patent |
Date Issued |
| 7369905 |
Method and apparatus for pressure and plasma control during transitions used to create graded in |
May 6, 2008 |
| A method and apparatus are provided for a graded PECVD process that continuously modulates a set of flow and pressure conditions while the plasma power is turned on and a film is being deposited. A feedback mechanism specific to a give deposition recipe is used to generate, optimize |
| 7369550 |
Method and apparatus for locking a table in a network switch |
May 6, 2008 |
| An apparatus and method are disclosed for locking a table within a network switch. The table is used to store entries that contain addresses of network stations connected to the network switch. A scheduler regulates access to the address table by allocating prescribed time slots during |
| 7072731 |
Starvation avoidance lot start agent (SALSA) |
July 4, 2006 |
| A system and method are provided for monitoring work in process ("WIP") in a manufacturing facility. The system and method utilize software objects to identify a bottleneck workstation and calculate a WIP value representing the amount of work approaching the bottleneck workstation. I |
| 7051336 |
Use of inheritance to allow concurrent programming |
May 23, 2006 |
| A process, architecture, and computer program product for using the inheritance features of an object-oriented system to enable multiple programmers to modify different behaviors of an object concurrently. A first method and a second method to be performed on the object are identifie |
| 7047517 |
System for integrating data between a plurality of software applications in a factory environmen |
May 16, 2006 |
| An architecture for integrating data between a plurality of software applications in a factory environment comprises a factory system and a domain application. The factory system comprises a domain object superclass and at least two first-level subclasses of the domain object supercl |
| 7033869 |
Strained silicon semiconductor on insulator MOSFET |
April 25, 2006 |
| An SOI substrate comprises a layer of strained silicon sandwiched between a dielectric layer and a layer of strained silicon. The substrate may be used to form a strained silicon SOI MOSFET having a gate electrode that extends through the silicon germanium layer to a channel region forme |
| 6948011 |
Alternate Register Mapping |
September 20, 2005 |
| A novel method of providing alternate access to a storage element for holding a data element in a network interface. The storage element is accessed via a first access path when the network interface operates with a first type of software, and via a second access path when a second type |
| 6927129 |
Narrow wide spacer |
August 9, 2005 |
| A method for fabricating a semiconductor device. Specifically, A method of manufacturing a semiconductor device comprising: depositing a first oxide layer over a periphery transistor comprising a gate stack, a drain side sidewall and a source side sidewall and over a core transistor comp |
| 6927113 |
Semiconductor component and method of manufacture |
August 9, 2005 |
| A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched through the hardmask a |
| 6919247 |
Method of fabricating a floating gate |
July 19, 2005 |
| A method of fabricating a floating gate for a semiconductor device is disclosed and provided. According to this method, an undoped polycrystalline silicon layer is deposited on a tunnel oxide layer. The undoped polycrystalline silicon layer has a first thickness. Moreover, a doped po |
| 6913958 |
Method for patterning a feature using a trimmed hardmask |
July 5, 2005 |
| In the formation of a semiconductor device, one or more hardmasks are formed during a process for patterning a device feature. One or more of the hardmasks is subjected to an isotropic etch to trim the hardmask prior to patterning an underlying layer. The trimmed hardmask layer is pr |
| 6891752 |
System and method for erase voltage control during multiple sector erase of a flash memory devic |
May 10, 2005 |
| A method for erasing a flash memory. In a flash memory device having multiple sectors a plurality of sectors is selected for erase (810). a subset of sectors is selected (815) and an erase pulse is applied simultaneously to all sectors in the subset (820). After the application of an |
| 6891390 |
Circuit analysis using electric field-induced effects |
May 10, 2005 |
| Circuitry within a semiconductor die is analyzed by applying an electric field without necessarily directly accessing the circuitry. According to an example embodiment of the present invention, an electric field is applied to a semiconductor die and used to stimulate circuitry therein. A |
| 6870258 |
Fixture suitable for use in coupling a lid to a substrate and method |
March 22, 2005 |
| A fixture suitable for coupling a lid to a substrate having a semiconductor chip coupled thereto and a method for coupling the lid to the substrate. A support structure has a cavity having a floor and a pedestal protruding from the floor. A guide extends from the support structure. A com |
| 6849530 |
Method for semiconductor gate line dimension reduction |
February 1, 2005 |
| To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely |
| 6849527 |
Strained silicon MOSFET having improved carrier mobility, strained silicon CMOS device, and meth |
February 1, 2005 |
| The mobility enhancement of a strained silicon layer is augmented through incorporation of carbon into a strained silicon lattice to which strain is also imparted by an underlying silicon germanium layer. The presence of the relatively small carbon atoms effectively increases the spacing |
| 6781429 |
Latch circuit with metastability trap and method therefor |
August 24, 2004 |
| Method and apparatus are provided for trapping metastability events to provide a metastable-free output signal. At least three successive values of an input signal are latched successively over a predetermined period which is less than half of a fundamental period of the input signal to |
| 6754779 |
SDRAM read prefetch from multiple master devices |
June 22, 2004 |
| Improved performance for data read operation is achieved in a read buffer that receives and stores requested information in response to read requests from multiple requesting master devices. A full cache line of data is read from the memory device into the read buffer in response to |
| 6751737 |
Multiple protected mode execution environments using multiple register sets and meta-protected i |
June 15, 2004 |
| A system is provided that contains multiple control register and descriptor table register sets so that an execution context switch between X86 protected mode operating systems can be performed with minimal processing overhead. Upon receipt of a protected instruction determined to be a |
| 6750544 |
Metallization system for use in a semiconductor component |
June 15, 2004 |
| A metallization system (10) suitable for use in a semiconductor component and a method for fabricating the metallization system (10). The metallization system (10) includes a dielectric material (20) disposed on a major surface (14) of a substrate (12). The dielectric material (20) c |
| 6710438 |
Enhanced chip scale package for wire bond dies |
March 23, 2004 |
| A chip scale package assembly comprises an integrated circuit die wire bonded to a carrier for mounting to a printed circuit board. The carrier comprises top and bottom ground planes thermally and electrically bonded together by a number of grounded thermal vias. The top ground plane |
| 6708075 |
Method and apparatus for utilizing integrated metrology data as feed-forward data |
March 16, 2004 |
| A method and an apparatus for performing feed-forward correction during semiconductor wafer manufacturing. A first process on a semiconductor wafer is performed. Integrated metrology data related to the first process of the semiconductor wafer is acquired. An integrated metrology fee |
| 6680507 |
Dual bit isolation scheme for flash memory devices having polysilicon floating gates |
January 20, 2004 |
| The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is prov |
| 6620639 |
Apparatus to evaluate hot carrier injection performance degradation and method therefor |
September 16, 2003 |
| A method and apparatus for evaluating the performance degradation of semiconductor integrated circuit devices due to hot carrier injection (HCI) is implemented. A device under test (DUT) is subject to a sequence of stress cycles. A stress condition is set on the device, for example, an |
| 6610550 |
Method and apparatus for correlating error model with defect data |
August 26, 2003 |
| A method and an apparatus for correlating error data with detect data. A semiconductor wafer in a first lot is processed. Defect data based upon analysis of the processed semiconductor wafer is acquired. Electrical test data based upon analysis of the processed semiconductor wafer is acq |
| 6593245 |
Silicon nitride etch process with critical dimension gain |
July 15, 2003 |
| A method for plasma etching of silicon nitride using a mixture of trifluoromethane and oxygen in a ratio of approximately 8 to 1 to selectively etch silicon nitride in preference to silicon dioxide and photoresist, resulting in critical dimension gain. |
| 6546513 |
Data processing device test apparatus and method therefor |
April 8, 2003 |
| A method and apparatus mechanism for testing data processing devices are implemented. The test mechanism isolates critical paths by correlating a scanning microscope image with a selected speed path failure. A trigger signal having a preselected value is generated at the start of each |
| 6512842 |
Composition based association engine for image archival systems |
January 28, 2003 |
| A method of analyzing defect images in a semiconductor manufacturing process wherein descriptors are assigned to images of defects caught during scanning of an inspection wafer. The images, assigned descriptors and linkage data are stored in a relational database. An operator can sel |
| 6506683 |
In-situ process for fabricating a semiconductor device with integral removal of antireflection a |
January 14, 2003 |
| A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) is fabricated by performing a number of process steps in-situ. Semiconductor devices having local interconnect areas are formed on a surface of a semiconductor substrate. |
| 6498454 |
Automatic battery recharging station for AGVs |
December 24, 2002 |
| The present invention provides AGV systems with automatic recharging and a central processor for control. The central processor monitors the charge states of the AGVs, assigns them to tasks, and can determines when to recharge the AGVs. The central processor can optimize the operation of |
| 6486038 |
Method for and device having STI using partial etch trench bottom liner |
November 26, 2002 |
| A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of (a) providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active la |
| 6463570 |
Apparatus and method for verifying process integrity |
October 8, 2002 |
| An apparatus and method for verifying a process step in the fabrication of an integrated circuit device is implemented. A ring oscillator is fabricated on the dice constituting the integrated circuit device being manufactured. The ring oscillator structure is adapted for sensitizing the |
| 6441349 |
System for facilitating uniform heating temperature of photoresist |
August 27, 2002 |
| A system and method for facilitating uniform heating temperature of a material is provided. The material may be a photoresist, a top or bottom anti-reflective coating, a low K dielectric material, SOG or other spin-on material. The system can include at least one heating element and a he |
| 6410350 |
Detecting die speed variations |
June 25, 2002 |
| An apparatus and method for detecting speed variations across a die, a flash field, i.e., multiple dies, and multiple flash fields. In one embodiment, a method comprises the step of inserting a plurality of functional circuits at strategic locations across a die or flash field or mul |
| 6407960 |
Arrangement for programming selected device registers during initialization from an external mem |
June 18, 2002 |
| An integrated device includes an external memory interface that includes address decoding logic configured for identifying a destination device register based on register address information retrieved from an external memory. The external memory interface, upon identifying the destinatio |
| 6407567 |
IC Device burn-in method and apparatus |
June 18, 2002 |
| An IC device bum-in system and method where a burn-in test motherboard is configured with a circuit environment like a customer level system motherboard. A stress software program is executed in a test controller which controls operational parameters to each IC device as well as dete |
| 6399467 |
Method of salicide formation |
June 4, 2002 |
| A method of forming a self-aligned silicide (salicide) with a screening oxide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present me |
| 6395609 |
Method for fabricating a bipolar junction transistor with tunneling current through the gate of |
May 28, 2002 |
| A MOSBJT (Metal Oxide Semiconductor Bipolar Junction Transistor) is formed to have both the higher current drive capability of the BJT and the smaller device area of the scaled down MOSFET. The MOSBJT includes a collector region and an emitter region comprised of a semiconductor mate |
| 6387786 |
Method of salicide formation by siliciding a gate area prior to siliciding a source and drain ar |
May 14, 2002 |
| The present invention relates to a method of forming a self-aligned silicide (salicide) by siliciding a gate area prior to siliciding a source and drain area and/or spacer formation. The method improves transistor speed by lowering the leakage current in the source and drain areas and |
| 6383822 |
Methodology for testing and qualifying an integrated circuit by measuring an operating frequency |
May 7, 2002 |
| A testing methodology for increasing the performance and reliability of integrated circuits ("chips") outputted from a manufacturing process, utilizes a method by which the operating frequency of the integrated circuit is measured when the Self-Timed Pulse Control parameter is adjust |
| 6365859 |
Processor IC performance metric |
April 2, 2002 |
| Parametric test data is taken on a sampled set of a particular integrated circuit (IC) using both an Automatic Test Equipment (ATE) tester and a system test motherboard. The parametric test data comprises maximum operating frequency, maximum operating temperature and minimum operating |
| 6353566 |
System and method for tracking sensing speed by an equalization pulse for a high density flash m |
March 5, 2002 |
| A sense amplifier output equalization circuit for a variable operating voltage high density flash memory device is disclosed. The equalization circuit compensates for the varying sensing speeds due to the varying operating voltages by variably adjusting the duration of an equalization |
| 6344994 |
Data retention characteristics as a result of high temperature bake |
February 5, 2002 |
| Dummy wordlines are provided between gaps of blocks of memory cells to compensate for higher charge loss at higher stress temperatures exhibited at edge wordlines of blocks of memory cells having large gaps. The dummy wordlines minimize the gap between the blocks. The dummy wordlines can |
| 6331953 |
Intelligent ramped gate and ramped drain erasure for non-volatile memory cells |
December 18, 2001 |
| A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes: applying a voltage across the gate and the first region i |
| 6329124 |
Method to produce high density memory cells and small spaces by using nitride spacer |
December 11, 2001 |
| The present invention relates to a method for forming an etch mask. A photoresist layer is patterned, wherein d.sub.1 is a smallest space dimension of an exposed area of a layer underlying the photoresist layer. An ARC layer under the photoresist layer is etched. A nitride layer is f |
| 6326313 |
Method and apparatus for partial drain during a nitride strip process step |
December 4, 2001 |
| A method of performing a nitride strip process step for a plurality of semiconductor wafers includes partially draining the chemical solution within a chemical bath after every nitride strip in which the oxide etch rate is within a specified range. If the oxide etch rate is above the |
| 6326251 |
Method of making salicidation of source and drain regions with metal gate MOSFET |
December 4, 2001 |
| A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A sil |
| 6323099 |
High k interconnect de-coupling capacitor with damascene process |
November 27, 2001 |
| An integrated circuit (IC) including integral, high k dielectric de-coupling capacitor constructed using a damascene process and contained within a single conductive layer of the IC structure. The IC comprises a substrate, a dielectric layer disposed over the substrate, and a conduct |
| 6322660 |
Apparatus and method for remote endpoint detection |
November 27, 2001 |
| A chromator for monitoring the end point of a plasma etching process is placed remotely from the window of a plasma etching chamber and is optically coupled to the window with a fiber optic cable bundle. The fiber optic cable bundle includes a first and a second bracket. Each bracket is |
| 6319843 |
Nitride surface passivation for acid catalyzed chemically amplified resist processing |
November 20, 2001 |
| In one embodiment, the present invention relates to a method of minimizing or preventing contamination of an acid catalyzed photoresist when using the acid catalyzed photoresist over a nitride containing film, involving contacting the nitride containing film with an oxidizing plasma comp |
