| Patent Number |
Title Of Patent |
Date Issued |
| RE37048 |
Field programmable digital signal processing array integrated circuit |
February 6, 2001 |
| A field programmable, digital signal processing integrated circuit is formed in a semiconductor die and includes an array of arithmetic logic (ALU) circuits. A user programmable interconnect architecture is superimposed on the array of ALU circuits. One or more interface circuits com |
| 7616508 |
Flash-based FPGA with secure reprogramming |
November 10, 2009 |
| A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or |
| 7616143 |
Reconfigurable delta sigma analog-to-digital converter and customized digital filters with embed |
November 10, 2009 |
| An integrated circuit includes at least one analog input. A sample/hold circuit is coupled to the at least one analog input. A reconfigurable delta-sigma ADC is coupled to the sample/hold circuit. A field programmable gate array is coupled to the reconfigurable delta-sigma ADC. A con |
| 7616026 |
System-on-a-chip integrated circuit including dual-function analog and digital inputs |
November 10, 2009 |
| An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconnect architecture pr |
| 7616025 |
Programmable logic device adapted to enter a low-power mode |
November 10, 2009 |
| A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a second low-power mode |
| 7613943 |
Programmable system on a chip |
November 3, 2009 |
| A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes program |
| 7603578 |
Programmable system on a chip for power-supply voltage and current monitoring and control |
October 13, 2009 |
| A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or |
| 7593268 |
Method for erasing programmable interconnect cells for field programmable gate arrays using reve |
September 22, 2009 |
| A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprised providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel |
| 7590000 |
Non-volatile programmable memory cell for programmable logic array |
September 15, 2009 |
| A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate tr |
| 7581117 |
Method for secure delivery of configuration data for a programmable logic device |
August 25, 2009 |
| Secure delivery of configuration data of an intellectual property (IP) core includes the steps of loading configuration data for the IP core into IP core space by an IP core provider, masking portions of the IP core space not loaded with configuration data in the loading configuratio |
| 7579895 |
Clock-generator architecture for a programmable-logic-based system on a chip |
August 25, 2009 |
| A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscilla |
| 7579869 |
Repeatable block producing a non-uniform routing architecture in a field programmable gate array |
August 25, 2009 |
| A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in |
| 7579868 |
Architecture for routing resources in a field programmable gate array |
August 25, 2009 |
| A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second p |
| 7573746 |
Volatile data storage in a non-volatile memory cell array |
August 11, 2009 |
| A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile |
| 7573093 |
Non-volatile two-transistor programmable logic cell and array layout |
August 11, 2009 |
| A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory t |
| 7560954 |
Programmable system on a chip for temperature monitoring and control |
July 14, 2009 |
| A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, |
| 7560952 |
Integrated circuit device having state-saving and initialization feature |
July 14, 2009 |
| An integrated circuit device has a state-saving feature and includes a programmable logic block, I/O pads, a dedicated register, at least one volatile memory block, a non-volatile memory block, a condition-sensing circuit for detecting at least one condition, A control circuit such as a |
| 7558967 |
Encryption for a stream file in an FPGA integrated circuit |
July 7, 2009 |
| A system for encrypting and decrypting data in a data stream for programming a Field Programmable Gate Array (FPGA). The system allows for an enable bit to be set for a gap in the data stream and the data is then encrypted from the beginning of the gap. A gap being bits in said data |
| 7558112 |
SRAM cell controlled by flash memory cell |
July 7, 2009 |
| First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit |
| 7557612 |
Block symmetrization in a field programmable gate array |
July 7, 2009 |
| An FPGA architecture has top, middle and low levels. The top level is an array of B16.times.16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routi |
| 7557611 |
Block level routing architecture in a field programmable gate array |
July 7, 2009 |
| An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16.times.16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of the B16.times.16 tile, and also associated with each of |
| 7554860 |
Nonvolatile memory integrated circuit having assembly buffer and bit-line driver, and method of |
June 30, 2009 |
| An assembly buffer and bitline driver circuit has two inverters cross-coupled to form an assembly buffer. A high-voltage latch is formed from cross-coupled high-voltage inverters. A first low-voltage n-channel MOS transistors is coupled to the high-voltage latch to selectively ground |
| 7549138 |
Parallel programmable antifuse field programmable gate array device (FPGA) and a method for prog |
June 16, 2009 |
| The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitio |
| 7548095 |
Isolation scheme for static and dynamic FPGA partial programming |
June 16, 2009 |
| An isolation scheme to permit partial programming of FPGA integrated circuits controlled by Flash memory cells includes a p-type semiconductor region. First and second spaced apart deep n-wells are disposed in the p-type semiconductor region. First and second p-wells are respectively |
| 7545169 |
FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitatio |
June 9, 2009 |
| An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connec |
| 7545168 |
Clock tree network in a field programmable gate array |
June 9, 2009 |
| A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA inclu |
| 7545166 |
Field-programmable gate array low voltage differential signaling driver utilizing two compliment |
June 9, 2009 |
| A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer. |
| 7543216 |
Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture |
June 2, 2009 |
| A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises providing serial data stream into the FPGA from an external source, loading data from the serial data stream into the configuration SRAM in response to address signals ge |
| 7538598 |
Circuit and method for supplying programming potential at voltages larger than BVDss of programm |
May 26, 2009 |
| A circuit for programming an antifuse coupled between a first node and a second node includes at least one transistor for supplying a programming potential V.sub.PP to the first node. A first transistor has a source coupled to a third node switchably coupleable between a potential of |
| 7538576 |
Non-volatile look-up table for an FPGA |
May 26, 2009 |
| A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2.sup.x=n as is known in the art. The output of the multiplexer |
| 7538382 |
Non-volatile two-transistor programmable logic cell and array layout |
May 26, 2009 |
| A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory t |
| 7538379 |
Non-volatile two-transistor programmable logic cell and array layout |
May 26, 2009 |
| A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory t |
| 7532035 |
Address transition detector for fast flash memory device |
May 12, 2009 |
| An address transition detector circuit includes an input node, an output node, a bandgap reference node, and P.sub.bias and N.sub.bias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel M |
| 7522453 |
Non-volatile memory with source-side column select |
April 21, 2009 |
| A non-volatile memory array segment includes an odd-select transistor having a drain coupled to an odd-source line and an even-select transistor having a drain coupled to an even-source line. Two segment-select transistors have drains coupled to the sources of different ones of the o |
| 7521960 |
Integrated circuit including programmable logic and external-device chip-enable override control |
April 21, 2009 |
| An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digi |
| 7516303 |
Field programmable gate array and microcontroller system-on-a-chip |
April 7, 2009 |
| A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are c |
| 7501872 |
Clock-generator architecture for a programmable-logic-based system on a chip |
March 10, 2009 |
| A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscilla |
| 7501681 |
Non-volatile two-transistor programmable logic cell and array layout |
March 10, 2009 |
| A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory t |
| 7499360 |
Flash/dynamic random access memory field programmable gate array |
March 3, 2009 |
| A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic |
| 7495473 |
Non-volatile look-up table for an FPGA |
February 24, 2009 |
| A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2.sup.x=n as is known in the art. The output of the multiplexer |
| 7493506 |
Programmable system on a chip for power-supply voltage and current monitoring and control |
February 17, 2009 |
| A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or |
| 7492183 |
Programmable system on a chip for power-supply voltage and current monitoring and control |
February 17, 2009 |
| A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or |
| 7492182 |
Non-volatile look-up table for an FPGA |
February 17, 2009 |
| A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2.sup.x=n as is known in the art. The output of the multiplexer |
| 7487376 |
Programmable system on a chip |
February 3, 2009 |
| A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes program |
| 7486538 |
Radiation tolerant SRAM bit |
February 3, 2009 |
| In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the seco |
| 7484113 |
Delay locked loop for an FPGA architecture |
January 27, 2009 |
| A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding |
| 7482835 |
Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable |
January 27, 2009 |
| A field-programmable gate array (FPGA) having an array of RAM memory cells comprising at least one row of RAM memory cells, each RAM cell of the at least one row of RAM memory cells coupled to a row driver line; a row decoder coupled to a first end of the row driver line of each at least |
| 7482218 |
Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated ci |
January 27, 2009 |
| A transistor formed on a semiconductor substrate of a first conductivity type in a well formed in the substrate and doped with the first conductivity type to an impurity level higher than that of the substrate. A drain doped to a second conductivity type opposite to said first conduc |
| 7477071 |
Three input field programmable gate array logic circuit configurable as a three input look up ta |
January 13, 2009 |
| A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least on |
| 7473960 |
Non-volatile two-transistor programmable logic cell and array layout |
January 6, 2009 |
| A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory t |
