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Actel Corporation Patents
Assignee:
Actel Corporation
Address:
Sunnyvale, CA
No. of patents:
457
Patents:


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Patent Number Title Of Patent Date Issued
RE37048 Field programmable digital signal processing array integrated circuit February 6, 2001
A field programmable, digital signal processing integrated circuit is formed in a semiconductor die and includes an array of arithmetic logic (ALU) circuits. A user programmable interconnect architecture is superimposed on the array of ALU circuits. One or more interface circuits com
8570819 Non-volatile memory array architecture optimized for hi-reliability and commercial markets October 29, 2013
A sense amplifier arrangement includes a first sense amplifier having a first input and a second input. A second sense amplifier has a first input and a second input. A switching circuit is configured to selectively couple the first input of the first sense amplifier to a first bit l
8289047 Architecture and interconnect scheme for programmable logic circuits October 16, 2012
An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs).
8269204 Back to back resistive random access memory cells September 18, 2012
A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conduc
8269203 Resistive RAM devices for programmable logic devices September 18, 2012
A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conduc
8258811 Enhanced field programmable gate array September 4, 2012
An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmab
8258567 Non-volatile two-transistor programmable logic cell and array layout September 4, 2012
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory t
8255854 Architecture and method for compensating for disparate signal rise and fall times by using polar August 28, 2012
A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprises creating a timing graph; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest
8244791 Fast carry lookahead circuits August 14, 2012
A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
8191021 Single event transient mitigation and measurement in integrated circuits May 29, 2012
A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises
8120955 Array and control method for flash based FPGA cell February 21, 2012
A push-pull non-volatile memory array includes memory cells with an n-channel non-volatile pull-down transistor in series with a p-channel volatile pull-up transistor. A non-volatile transistor row line is associated with each row of the array and is coupled to the control gates of e
8085064 Logic module including versatile adder for FPGA December 27, 2011
A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory
8067959 Programmable delay line compensated for process, voltage, and temperature November 29, 2011
A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each su
8040151 Programmable logic device with programmable wakeup pins October 18, 2011
A programmable logic device (PLD) adapted to enter a low-power or sleep mode with programmable wakeup pins in a wakeup group of pins is disclosed. Wake on a single pin change, wake on vector, and wake on a single pin transition are supported. The approach is to select the actively pa
7977970 Enhanced field programmable gate array July 12, 2011
An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmab
7956404 Non-volatile two-transistor programmable logic cell and array layout June 7, 2011
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory t
7944238 (N+1) input flip-flop packing with logic in FPGA architectures May 17, 2011
A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop
7941685 Delay locked loop for an FPGA architecture May 10, 2011
A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding
7937647 Error-detecting and correcting FPGA architecture May 3, 2011
A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a
7937601 Programmable system on a chip May 3, 2011
A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes program
7932745 Inverting flip-flop for use in field programmable gate arrays April 26, 2011
A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input ter
7932744 Staggered I/O groups for integrated circuits April 26, 2011
An I/O scheme for an integrated circuit includes a group layout cell. The group layout cell includes a plurality of signal I/O pads. A driver circuit is coupled to each signal I/O pad. The group layout cell also includes two I/O driver-circuit power-supply pads. ESD protection circui
7929345 Push-pull memory cell configured for simultaneous programming of n-channel and p-channel non-vol April 19, 2011
A method of for programming a push-pull memory cell to simultaneously program a p-channel non-volatile transistor and an n-channel non-volatile transistor includes driving to 0v wordlines for any row in which programming of memory cells is to be inhibited; driving to a positive volta
7924053 Clustered field programmable gate array architecture April 12, 2011
A logic cluster for a field programmable gate array integrated circuit device is disclosed. The cluster comprises a plurality of functional blocks and three levels of routing multiplexers. External signals enter the logic cluster primarily at the third level multiplexers with a few s
7924052 Field programmable gate array architecture having Clos network-based input interconnect April 12, 2011
A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the nu
7924051 Programmable logic device with a microcontroller-based control system April 12, 2011
A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device. The computer program product comprises first instructions for initializing the device, second instructions for reading programming
7919979 Field programmable gate array including a non-volatile user memory and method for programming April 5, 2011
An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may also be used to s
7919977 Circuits and methods for testing FPGA routing switches April 5, 2011
An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the swit
7915918 Method and apparatus for universal program controlled bus architecture March 29, 2011
An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality
7915665 Non-volatile two-transistor programmable logic cell and array layout March 29, 2011
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory t
7911226 Power-up and power-down circuit for system-on-a-chip integrated circuit March 22, 2011
A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad.
7910436 Isolated-nitride-region non-volatile memory cell and fabrication method March 22, 2011
An isolated-nitride-region non-volatile memory cell is formed in a semiconductor substrate. Spaced-apart source and drain regions are disposed in the semiconductor substrate forming a channel therebetween. An insulating region is disposed over the semiconductor substrate. A gate is d
7906805 Reduced-edge radiation-tolerant non-volatile transistor memory cells March 15, 2011
An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom
7898018 Non-volatile two-transistor programmable logic cell and array layout March 1, 2011
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory t
7886261 Programmable logic device adapted to enter a low-power mode February 8, 2011
A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a second low-power mode
7886130 Field programmable gate array and microcontroller system-on-a-chip February 8, 2011
A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are c
7885122 Flash-based FPGA with secure reprogramming February 8, 2011
A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or
7884640 PLD providing soft wakeup logic February 8, 2011
A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always
7884636 Single event transient mitigation and measurement in integrated circuits February 8, 2011
A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises
7872497 Flexible carry scheme for field programmable gate arrays January 18, 2011
A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input c
7859302 Programmable system on a chip for power-supply voltage and current monitoring and control December 28, 2010
A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or
7839681 Push-pull FPGA cell November 23, 2010
A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transi
7838944 Non-volatile programmable memory cell and array for programmable logic array November 23, 2010
A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate tr
7830173 Method and apparatus for universal program controlled bus architecture November 9, 2010
An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality
7816946 Inverting flip-flop for use in field programmable gate arrays October 19, 2010
A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input ter
7804321 Circuits and methods for testing FPGA routing switches September 28, 2010
An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the swit
7774665 Apparatus for testing a phrase-locked loop in a boundary scan enabled device August 10, 2010
An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver mo
7772879 Logic module including versatile adder for FPGA August 10, 2010
A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory
7772874 Single event transient mitigation and measurement in integrated circuits August 10, 2010
A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises
7768810 Radiation tolerant SRAM bit August 3, 2010
In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the seco
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