| Patent Number |
Title Of Patent |
Date Issued |
| RE37048 |
Field programmable digital signal processing array integrated circuit |
February 6, 2001 |
| A field programmable, digital signal processing integrated circuit is formed in a semiconductor die and includes an array of arithmetic logic (ALU) circuits. A user programmable interconnect architecture is superimposed on the array of ALU circuits. One or more interface circuits com |
| 7473960 |
Non-volatile two-transistor programmable logic cell and array layout |
January 6, 2009 |
| A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory t |
| 7463061 |
Apparatus and method for reducing leakage of unused buffers in an integrated circuit |
December 9, 2008 |
| A reduced-leakage interconnect circuit includes a buffer having an input and an output, at least one multiplexer transistor coupled between a multiplexer input node and the input of the buffer, and a fixed-state multiplexer transistor coupled between a fixed-state multiplexer input n |
| 7459772 |
Face-to-face bonded I/O circuit die and functional logic circuit die system |
December 2, 2008 |
| An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. |
| 7459763 |
Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material |
December 2, 2008 |
| A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group |
| 7446560 |
Programmable system on a chip for temperature monitoring and control |
November 4, 2008 |
| A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, |
| 7446378 |
ESD protection structure for I/O pad subject to both positive and negative voltages |
November 4, 2008 |
| An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing |
| 7444456 |
SRAM bus architecture and interconnect to an FPGA |
October 28, 2008 |
| An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a |
| 7443191 |
Apparatus and method of error detection and correction in a radiation-hardened static random acc |
October 28, 2008 |
| The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Er |
| 7439818 |
Voltage-and temperature-compensated RC oscillator circuit |
October 21, 2008 |
| An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting inp |
| 7434080 |
Apparatus for interfacing and testing a phase locked loop in a field programmable gate array |
October 7, 2008 |
| An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver mo |
| 7432733 |
Multi-level routing architecture in a field programmable gate array having transmitters and rece |
October 7, 2008 |
| A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality |
| 7430137 |
Non-volatile memory cells in a field programmable gate array |
September 30, 2008 |
| A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor ha |
| 7426667 |
Apparatus and method for initializing an integrated circuit device and activating a function of |
September 16, 2008 |
| An apparatus for generating a function activation signal to activate a function in an integrated circuit device comprises a power-on circuit receiving a power input and initializing and generating a test activation signal, a test circuit receiving the test activation signal and gener |
| 7426665 |
Tileable field-programmable gate array architecture |
September 16, 2008 |
| A method for testing FPGA routing circuitry having a plurality of first sets of tracks having programmably connectable individual track segments includes providing a global control signal to simultaneously turn on all of the programmable elements in at least two of the first sets of trac |
| 7423451 |
System-on-a-chip integrated circuit including dual-function analog and digital inputs |
September 9, 2008 |
| An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconnect architecture pr |
| 7421605 |
Programmable system on a chip for power-supply voltage and current monitoring and control |
September 2, 2008 |
| A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or |
| 7414428 |
Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an F |
August 19, 2008 |
| A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first configurable circuit elements external to the FPGA fabric, and a plurality of second configu |
| 7414427 |
Integrated multi-function analog circuit including voltage, current, and temperature monitor and |
August 19, 2008 |
| An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a third I/O pad. At l |
| 7409664 |
Architecture and interconnect scheme for programmable logic circuits |
August 5, 2008 |
| An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and a |
| 7408815 |
SRAM cell controlled by flash memory cell |
August 5, 2008 |
| First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit |
| 7408383 |
FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitatio |
August 5, 2008 |
| An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connec |
| 7403411 |
Deglitching circuits for a radiation-hardened static random access memory based programmable arc |
July 22, 2008 |
| A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of |
| 7400283 |
Mixed signal system-on-a-chip integrated simultaneous multiple sample/hold circuits and embedded |
July 15, 2008 |
| An integrated circuit includes a plurality of circuit groups, each circuit group containing a plurality of analog inputs, a buffer, a sample/hold circuit and a comparator. Each buffer has an input to which any of the analog inputs in its group may be programmably connected. The output of |
| 7400185 |
Circuit and method for supplying programming potential at voltages larger than BVDss of programm |
July 15, 2008 |
| A circuit for programming an antifuse coupled between a first node and a second node includes at least one transistor for supplying a programming potential V.sub.PP to the first node. A first transistor has a source coupled to a third node switchably coupleable between a potential of |
| 7394289 |
Synchronous first-in/first-out block memory for a field programmable gate array |
July 1, 2008 |
| The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated |
| 7394286 |
Field programmable gate array long line routing network |
July 1, 2008 |
| A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of a first set of routing |
| 7393722 |
Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material |
July 1, 2008 |
| A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group |
| 7390726 |
Switching ratio and on-state resistance of an antifuse programmed below 5 mA and having a Ta or |
June 24, 2008 |
| A metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. An insulating layer is disposed above a lower metal interconnect layer. The insulating layer includes a via formed therethrough containing a tungsten plug in electrical contact with |
| 7389487 |
Dedicated interface architecture for a hybrid integrated circuit |
June 17, 2008 |
| An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC. |
| 7385421 |
Block symmetrization in a field programmable gate array |
June 10, 2008 |
| An FPGA architecture has top, middle and low levels. The top level is an array of B16.times.16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routi |
| 7385420 |
Repeatable block producing a non-uniform routing architecture in a field programmable gate array |
June 10, 2008 |
| A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in |
| 7385419 |
Dedicated input/output first in/first out module for a field programmable gate array |
June 10, 2008 |
| A field programmable gate array architecture having a plurality of input/output pads. The architecture comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory |
| 7385418 |
Non-volatile memory architecture for programmable-logic-based system on a chip |
June 10, 2008 |
| A programmable system-on-a-chip integrated circuit device includes a programmable logic block. A digital input/output circuit block is coupled to the programmable logic block. A SRAM block is coupled to the programmable logic block. At least one non-volatile memory block is coupled t |
| 7382156 |
Method and apparatus for universal program controlled bus architecture |
June 3, 2008 |
| An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality |
| 7382155 |
Enhanced field programmable gate array |
June 3, 2008 |
| An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmab |
| 7378867 |
Field-programmable gate array low voltage differential signaling driver utilizing two compliment |
May 27, 2008 |
| A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer. |
| 7375553 |
Clock tree network in a field programmable gate array |
May 20, 2008 |
| A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA inclu |
| 7368789 |
Non-volatile programmable memory cell and array for programmable logic array |
May 6, 2008 |
| A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate tr |
| 7366008 |
Radiation tolerant SRAM bit |
April 29, 2008 |
| In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the seco |
| 7365567 |
Three input field programmable gate array logic circuit configurable as a three input look up ta |
April 29, 2008 |
| A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least on |
| 7365565 |
Programmable system on a chip for power-supply voltage and current monitoring and control |
April 29, 2008 |
| A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or |
| 7362610 |
Programming method for non-volatile memory and non-volatile memory-based programmable logic devi |
April 22, 2008 |
| A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming |
| 7362131 |
Integrated circuit including programmable logic and external-device chip-enable override control |
April 22, 2008 |
| An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digi |
| 7360195 |
Block level routing architecture in a field programmable gate array |
April 15, 2008 |
| An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16.times.16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16.times.16 tile, and also associated with each of |
| 7358601 |
Architecture for face-to-face bonding between substrate and multiple daughter chips |
April 15, 2008 |
| An integrated circuit system includes a first integrated circuit die and a family of second integrated circuit dice. The first integrated circuit die have input/output circuits disposed thereon and further have a first array of face-to-face bonding structures disposed on a first face |
| 7358589 |
Amorphous carbon metal-to-metal antifuse with adhesion promoting layers |
April 15, 2008 |
| A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over s |
| 7352206 |
Integrated circuit device having state-saving and initialization feature |
April 1, 2008 |
| An integrated circuit device has a state-saving feature and includes a programmable logic block, I/O pads, a dedicated register, at least one volatile memory block, a non-volatile memory block, a condition-sensing circuit for detecting at least one condition, A control circuit such as a |
| 7342832 |
Bit line pre-settlement circuit and method for flash memory sensing scheme |
March 11, 2008 |
| A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line |
| 7342416 |
Tileable field-programmable gate array architecture |
March 11, 2008 |
| An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals |
