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Acatel Corporation Patents |
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Assignee: Acatel Corporation
Address: Sunnyvale, CA
No. of patents: 1
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 6268743 |
Block symmetrization in a field programmable gate array |
July 31, 2001 |
| An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16.times.16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16.times.16 tile, and also associated with each of |
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