| Patent Number |
Title Of Patent |
Date Issued |
| RE39003 |
Closed caption support with timewarp |
March 7, 2006 |
| Method of providing closed captioned data to a television viewer comprised of detecting closed captioned data signals transmitted in conjunction with a television signal, decoding the data signals to caption display signals, and displaying the caption display signals on an auxiliary |
| RE38610 |
Host CPU independent video processing unit |
October 5, 2004 |
| The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, |
| D494544 |
High density interconnection device |
August 17, 2004 |
|
| 7624123 |
Image processing system and method |
November 24, 2009 |
| An image processing system and method receives one or more digital images in the form of image data, including selected object data of a digital image, and determines, by an electronic recognition process, if a recognition match is available between the selected object data of the di |
| 7613346 |
Compositing in multiple video processing unit (VPU) systems |
November 3, 2009 |
| Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is cou |
| 7612783 |
Advanced anti-aliasing with multiple graphics processing units |
November 3, 2009 |
| A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU re |
| 7596743 |
Method and apparatus for error management |
September 29, 2009 |
| To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involv |
| 7594265 |
System for preventing unauthorized access to sensitive data and a method thereof |
September 22, 2009 |
| A method and system for prevention of unauthorized access to multimedia data are disclosed herein. A tamper-resistant system having a software driver, a peripheral device, and a system memory is used to encrypt sensitive routines used by the software driver. The software driver is us |
| 7594069 |
Method and apparatus for single instruction multiple data caching |
September 22, 2009 |
| An apparatus and method for single instruction multiple data caching includes a memory access request generator operative to receive a primary access request. The method and apparatus further includes a cache controller coupled to the memory access request generator, wherein the cach |
| 7583755 |
Systems, methods, and apparatus for mitigation of nonlinear distortion |
September 1, 2009 |
| A method among the embodiments includes calculating a value of a parameter of a nonlinear model of a signal as transmitted into a transmission channel, and applying the calculated value to obtain an estimate of data values carried by the signal. Applications to multicarrier signals are |
| 7573531 |
Rapid channel signal identification |
August 11, 2009 |
| An apparatus, for use in a receiver configured to receive electronic signals, for identifying digital signals that are available for reception, includes a timing recovery device configured to receive an incoming signal, related to a transmitted signal, the incoming signal having a fi |
| 7568193 |
Method and apparatus for static single assignment form dead code elimination |
July 28, 2009 |
| A method and apparatus for SSA dead code elimination includes examining a first instruction off a worklist, wherein the first instruction includes previous link and a write mask and the first instruction is an SSA instruction. The method and apparatus further includes examining at least |
| 7568191 |
Method and apparatus for superword register value numbering |
July 28, 2009 |
| A method and apparatus for superword register value numbering includes hashing an operation code and the value numbers of a plurality of sources to generate a flint hash value. The method and apparatus further includes retrieving an operation value number from the first hash table based |
| 7558933 |
Synchronous dynamic random access memory interface and method |
July 7, 2009 |
| A memory interface allows access SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n(n>1) column memory addresses from the received column address. The interface accesses |
| 7558337 |
Systems, methods, and apparatus for impulse noise mitigation |
July 7, 2009 |
| A method of signal processing according to one of several embodiments includes estimating a deterministic component of a received signal. The estimating is based on an estimated response of a transmission channel. Based on the estimated deterministic component, a non-deterministic co |
| 7551699 |
Method and apparatus for controlling a smart antenna using metrics derived from a single carrier |
June 23, 2009 |
| A method for selecting an antenna direction setting for optimum signal reception prior to channel equalization provides a set of metrics, referred to as channel quality metrics (CQM), that characterize the quality of the received signal for a given antenna setting and a generic algor |
| 7551679 |
Symmetrical data signal processing |
June 23, 2009 |
| In a digital communications receiver configured to receive, via a communications channel, a received first signal representing a sequence of symbols, each symbol being encoded to be representative of data bits, a method of processing the received signal includes adjusting a magnitude |
| 7551177 |
Methods and apparatus for retrieving and combining samples of graphics information |
June 23, 2009 |
| Disclosed are methods and apparatus for accomplishing the fetching or sampling of channels of pixels or texels such as neighboring pixels or texels or non-neighboring pixels or texels in a simultaneous operation in order to achieve optimization of the performance of a texture pipeline. |
| 7530007 |
Iterative decoding of packet data |
May 5, 2009 |
| A receiver employs iterative decoding of packet data, where the packet data represents a data frame encoded with at least two logical dimensions. A logical dimension refers to a layer, or sub-layer, of a layered network architecture. Consequently, a first logical dimension of encodin |
| 7526427 |
System and method for reception, processing and transmission of digital audio stream |
April 28, 2009 |
| A system and methods are described for processing digital audio stream data from received transport streams. A transport stream parser identifies particular transport packets related to audio stream data. The transport stream parser enables audio parser and provides packet identifier |
| 7509515 |
Method and system for communicated client phase information during an idle period of a data bus |
March 24, 2009 |
| A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data li |
| 7499545 |
Method and system for dual link communications encryption |
March 3, 2009 |
| A method and systems are provided for creating an authentication of secure communications between a software video driver and a video display. A video driver transmitting digital video data deemed high-bandwidth digital content, to a display, performs authentication to determine if a |
| 7495477 |
Apparatus and methods for self-biasing differential signaling circuitry having multimode output |
February 24, 2009 |
| The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and |
| 7487378 |
Asymmetrical IO method and system |
February 3, 2009 |
| An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and |
| 7486297 |
Method and apparatus for image processing in a handheld device |
February 3, 2009 |
| The present invention provides a method and apparatus for image processing using a graphics processor in a handheld device including a first memory device receiving a video input signal containing encoded video frame having a plurality of portions of encoded video frame data. The first |
| 7477325 |
Audio/video separator |
January 13, 2009 |
| An audio/video separator provides a high-performance and cost-effective solution to analog TV reception with only one A/D converter and a minimum of analog IF components. The apparatus may operate on a digitized TV signal and, when integrated with a digital video processor, process video |
| 7447869 |
Method and apparatus for fragment processing in a virtual memory system |
November 4, 2008 |
| A method and apparatus for fragment processing in a virtual memory system are described. Embodiments of the invention include a coprocessor comprising a virtual memory system for accessing a physical memory. Page table logic and fragment processing logic scan a page table having a fi |
| 7434034 |
SIMD processor executing min/max instructions |
October 7, 2008 |
| The result of eight find_min_16 of lookup-min_16, find_max_l6x, lookup_max_16 instructions may be stored in memory storage units of operand storage 24, using SIMD at addressing techniques detailed in U.S. patent application Ser. No. 10/929,992, filed Aug. 30, 2004 and entitled SIMD P |
| 7434024 |
SIMD processor with register addressing, buffer stall and methods |
October 7, 2008 |
| A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. |
| 7427990 |
Data replacement method and circuit for motion prediction cache |
September 23, 2008 |
| A system for decoding a video bitstream and a method for replacing image data in a motion prediction cache are described. For each of the cache lines, a tag distance between pixels stored in the cache line and uncached pixels that are to be stored in the cache is calculated. The calc |
| 7423644 |
Method and apparatus for dual pass adaptive tessellation |
September 9, 2008 |
| A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit |
| 7394500 |
World wide analog television signal receiver |
July 1, 2008 |
| A TV signal reception system is configured to include adjustable components and a controller to provide instructions to adjust the adjustable components. By pre-arranging configurations corresponding to multiple variants of world wide TV standards, the TV signal reception system may |
| 7392411 |
Systems and methods for dynamic voltage scaling of communication bus to provide bandwidth based |
June 24, 2008 |
| Systems and methods for dynamic power management of electronic devices are disclosed. In one form, a system employing dynamic power management for electronic devices includes a central processing unit operable to process information via a communication bus. The system includes a clock |
| 7386410 |
Closed loop controlled reference voltage calibration circuit and method |
June 10, 2008 |
| A variable reference voltage circuit controllable in closed loop, for calibrating off-chip and on-chip drivers, margining and optimizing a reference voltage, for interfaces such as DDR2 or any other suitable interface. In one example, the on-chip variable reference voltage circuit, c |
| 7385545 |
Reduced component digital to analog decoder and method |
June 10, 2008 |
| An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be u |
| 7385534 |
Methods and apparatus for processing variable length coded data |
June 10, 2008 |
| An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient |
| 7376692 |
Method and system for receiving and framing packetized data |
May 20, 2008 |
| In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation |
| 7366961 |
Method and system for handling errors |
April 29, 2008 |
| In accordance with a specific aspect of the present disclosure, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. In addition, |
| 7362583 |
Thermal management device for multiple heat producing devices |
April 22, 2008 |
| A thermal management device for a circuit substrate having at least a first heat generating component and at least a second heat generating component, the thermal management device includes a first thermal spreader and a second thermal spreader. The second thermal spreader is mountab |
| 7356823 |
Method for displaying single monitor applications on multiple monitors driven by a personal comp |
April 8, 2008 |
| A direct access driver solves limitations of DirectX operation under the Microsoft architecture when using multiple monitors. The direct access driver allows applications employing DirectX application program interfaces to use hardware acceleration without display errors on the monit |
| 7345510 |
Method and apparatus for generating a reference signal and generating a scaled output signal bas |
March 18, 2008 |
| An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first |
| 7343512 |
Controlling clock rates of an integrated circuit including generating a clock rate control param |
March 11, 2008 |
| Systems and methods for controlling clock rates of circuits are provided. The systems and methods, collectively referred to as clock rate control, generate a clock rate control parameter from data of one or more fuses. The clock rate control detects any overclocked signal of received clo |
| 7343508 |
Dynamic clock control circuit for graphics engine clock and memory clock and method |
March 11, 2008 |
| A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level of memory. In response, the variable clock control information generator produces graphic |
| 7342981 |
Digital receiver having adaptive carrier recovery circuit |
March 11, 2008 |
| A digital receiver, that may be used to receive VSB/QAM digital television signals, includes an adaptive fine carrier recovery circuit that compensates for deviations in the carrier frequency or phase. The carrier recovery circuit de-rotates a signal including phase errors. Estimations |
| 7337346 |
Method and apparatus for fine tuning a memory interface |
February 26, 2008 |
| A method and apparatus for fine tuning a memory interface includes receiver operative to receive an input signal. The method and apparatus includes a clock counter operative to calculate a time value based upon the timed sequence determined by the reception of the input signal. The m |
| 7336318 |
Synthetic insertion of clear codes during video program changes |
February 26, 2008 |
| An apparatus and method for facilitating program changes. The apparatus and method include a controller for detecting a change program request and for outputting change event data when a change event is detected. A non-active video information replacement module is coupled to the con |
| 7336284 |
Two level cache memory architecture |
February 26, 2008 |
| A memory architecture for use in a graphics processor including a main memory, a level one (L1) cache and a level two (L2) cache, coupled between the main memory and the L1 cache is disclosed. The L2 cache stores overlapping requests to the main memory before the requested informatio |
| 7336275 |
Pseudo random number generator and method |
February 26, 2008 |
| A pseudo random number generator that generates a plurality of intermediate values, where each successive intermediate value is based, at least in part, on one of the succeeding intermediate values, where a final value based on a subset of the plurality of intermediate values. In app |
| 7336212 |
Apparatus and methods for measurement of analog voltages in an integrated circuit |
February 26, 2008 |
| The present disclosure relates to apparatus and methods for measurement of analog voltages in an integrated circuit. In particular, the apparatus includes an on-chip digital-to-analog converter configured to receive a variable digital input code and output a corresponding analog voltage |
| 7327369 |
Graphics processing architecture employing a unified shader |
February 5, 2008 |
| A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the pluralit |
