| Patent Number |
Title Of Patent |
Date Issued |
| 5297258 |
Data logging for hard disk data storage systems |
March 22, 1994 |
| A data log for use with conventional hard disk subsystems or other data storage subsystems provides a system to minimize delays caused in a computer system due to the input/output systems, such as hard disks. The data log is preferably one or more hard disks, or any other non-volatile |
| 5280283 |
Memory mapped keyboard controller |
January 18, 1994 |
| A memory mapped keyboard controller within a peripheral controller for use in an Industry Standard Architecture (ISA) computer provides a method and apparatus for efficiently monitoring and reading a keyboard switch matrix. In a first mode of operation, the controller activates all the c |
| 5263668 |
Computer pedestal |
November 23, 1993 |
| A computer pedestal for stably supporting a computer component in an upright orientation can be nestably engaged with other like pedestals to permit side-by-side stowage of a plurality of computer components. The pedestal has a flat parallelepiped-shaped base, and at least one stabil |
| 5261114 |
Method and apparatus for providing down-loaded instructions for execution by a peripheral contro |
November 9, 1993 |
| A method and apparatus for downloading instructions and other information to a peripheral controller for use in an Industry Standard Architecture (ISA) compatible computer provides a system which downloads instructions from the ISA compatible computer to an random access memory (RAM) |
| 5247643 |
Memory control circuit for optimizing copy back/line fill operation in a copy back cache system |
September 21, 1993 |
| A memory system for use with a copy back cache system includes a control circuit that reduces the amount of time to complete a copy back/line fill operation in which a first line of data from the cache is stored in the memory system and then a second line of data is retrieved from the me |
| 5247642 |
Apparatus for determining cacheability of a memory address to provide zero wait state operation |
September 21, 1993 |
| A computer system includes an Intel 80486 microprocessor having an internal cache memory and a local memory tightly coupled to the microprocessor that can respond to memory accesses without requiring the microprocessor to execute a wait state. An external cache memory system is provided |
| 5237692 |
Internal interrupt controller for a peripheral controller |
August 17, 1993 |
| An interrupt driven peripheral controller for use in an Industry Standard Architecture (ISA) compatible computer provides a system to minimize power consumption as compared to conventional peripheral controllers. The peripheral controller utilizes an internal interrupt controller which |
| 5191657 |
Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry sta |
March 2, 1993 |
| A computer system includes a microprocessor that is electrically connected to a first synchronous bus operating in synchronism with a first clock signal at a first clock frequency. A second synchronous bus operates in synchronism with a second clock signal at a second clock frequency and |
| 5187425 |
Rechargeable battery controller |
February 16, 1993 |
| A battery monitor system is disclosed comprising a microcontroller which monitors voltage inputs from a power adapter and a rechargeable battery. The power adapter includes a voltage source and a current source which outputs two current levels. A thermistor is thermally coupled to the |
| 5181029 |
Electronic keyboard template |
January 19, 1993 |
| An electronic keyboard template for use with software applications programs is responsive to command signals transmitted by designated function keys on a computer keyboard. The template includes an LCD display screen for displaying icons representative of operations performed by the func |
| 5132635 |
Serial testing of removable circuit boards on a backplane bus |
July 21, 1992 |
| A system for controlling daisy-chain testing of removable printed circuit boards installed along a backplane bus facilitates the use of serial testing methods for circuit boards which are designed according to boundary-scan testing standards. The system automatically controls propaga |
| 5109517 |
System for selectively controlling slots in an IBM-AT/NEC 9801 dual-compatible computer |
April 28, 1992 |
| A system for selectively controlling individual expansion slots in an IBM-AT/NEC 9801 dual compatible computer provides automatic control for the individual ISA bus expansion slots in the computer. This facilitates the use of an Industry Standard Architecture (ISA) bus and ISA (AT) type |
| 5083049 |
Asynchronous circuit with edge-triggered inputs |
January 21, 1992 |
| An asynchronous circuit utilizes toggle flip-flops to receive a plurality of asynchronous input signals. The input signals are applied to the edge-triggered clock inputs of the toggle flip-flops so that outputs of the toggle flip-flops and other logic signals within the asynchronous |
| 5038308 |
Compact system unit for personal computers |
August 6, 1991 |
| A compact system unit for personal computers wherein system hardware components are closely integrated and packed resulting in an effective utilization of space. Such compact integration of hardware is facilitated by the arrangement of system hardware components co-planar with each o |
| 4987529 |
Shared memory bus system for arbitrating access control among contending memory refresh circuits |
January 22, 1991 |
| An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycle |
| 4973860 |
Circuit for synchronizing an asynchronous input signal to a high frequency clock |
November 27, 1990 |
| A circuit for synchronizing an asynchronous input signal with an internal time base clock operates at a high frequency. The circuit includes an input flip-flop that receives the input signal and an output flip-flop that provides an output signal that is synchronized with the internal tim |
| 4954929 |
Multi-layer circuit board that suppresses radio frequency interference from high frequency signa |
September 4, 1990 |
| A multi-layer printed circuit board is constructed to suppress radio frequency interference (RFI) generated by high frequency clock and data signals therein. Suppression is achieved by positioning clock lines carrying the clock signal on a first voltage reference layer proximate to a |
