| Patent Number |
Title Of Patent |
Date Issued |
| 7411289 |
Integrated circuit package with partially exposed contact pads and process for fabricating the s |
August 12, 2008 |
| A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconduc |
| 7410830 |
Leadless plastic chip carrier and method of fabricating same |
August 12, 2008 |
| A process for fabricating a leadless plastic chip carrier includes providing a leadframe including a plurality of contacts circumscribing a void; fixing a heat sink to the contacts of the leadframe using an intermediate non-electrically conductive adhesive such that the heat sink spa |
| 7381588 |
Shielded integrated circuit package |
June 3, 2008 |
| An integrated circuit package is provided. The package includes a die attach pad having a first side and a second side. A first semiconductor die is mounted to the first side of the die attach pad, a plurality of contact pads disposed in close proximity to the first semiconductor die. |
| 7372151 |
Ball grid array package and process for manufacturing same |
May 13, 2008 |
| A process for manufacturing an integrated circuit package includes forming a plurality of solder balls on a first surface of a substrate and mounting a semiconductor die to the substrate such that bumps of the semiconductor die are electrically connected to conductive traces of the s |
| 7371610 |
Process for fabricating an integrated circuit package with reduced mold warping |
May 13, 2008 |
| A process for fabricating an integrated circuit package includes mounting a semiconductor die on a first surface of a metal carrier and forming electrical connections between the semiconductor die and ones of a plurality of contacts on the metal carrier. Next, using a molding materia |
| 7358119 |
Thin array plastic package without die attach pad and process for fabricating the same |
April 15, 2008 |
| A process for fabricating an integrated circuit package. Metal is plated up on a substrate to provide a plurality of contact pads and a plurality of fiducial markings on a periphery of the contacts. A transparent mask is selectively deposited on the substrate, over the fiducial markings. |
| 7348663 |
Integrated circuit package and method for fabricating same |
March 25, 2008 |
| A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the subs |
| 7344920 |
Integrated circuit package and method for fabricating same |
March 18, 2008 |
| A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the subs |
| 7342305 |
Thermally enhanced cavity-down integrated circuit package |
March 11, 2008 |
| A cavity-down ball grid includes a flexible circuit tape including a flexible tape laminated to a conductor layer. The flexible circuit tape has an aperture therein. A thermally conductive heat spreader is fixed to a first surface of the flexible circuit tape and the heat spreader has a |
| 7315080 |
Ball grid array package that includes a collapsible spacer for separating die adapter from a hea |
January 1, 2008 |
| A ball grid array package is manufactured by mounting a semiconductor die to a first surface of a substrate and mounting a die adapter to the semiconductor die. The semiconductor die is wire bonded to ones of conductive traces of the substrate. A collapsible spacer is mounted to the |
| 7271032 |
Leadless plastic chip carrier with etch back pad singulation |
September 18, 2007 |
| A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, |
| 7270867 |
Leadless plastic chip carrier |
September 18, 2007 |
| A process for fabricating a leadless plastic chip carrier includes selectively depositing a plurality of base layers on a first surface of a base of a leadframe strip to at least partially define a die attach pad and at least one row of contact pads. At least one further layer is sel |
| 7247526 |
Process for fabricating an integrated circuit package |
July 24, 2007 |
| A process for fabricating an integrated circuit package. At least a first side of a leadframe strip is selectively etched to define portions of a die attach pad and at least one row of contacts adjacent the die attach pad. A carrier strip is laminated to the first side of the leadframe |
| 7232755 |
Process for fabricating pad frame and integrated circuit package |
June 19, 2007 |
| A process for fabricating a pad frame for an integrated circuit package includes building up metal on selective portions of a first side of a substrate to define a plurality of contact pads disposed in a first layer of dielectric material, depositing a metal seed layer on an exposed side |
| 7226811 |
Process for fabricating a leadless plastic chip carrier |
June 5, 2007 |
| A process for fabricating a leadless plastic chip carrier includes laminating a first metal strip to a second metal strip to form a leadframe strip, selectively etching the first metal strip to define at least a row of contact pads, mounting a semiconductor die to either a die attach |
| 7224048 |
Flip chip ball grid array package |
May 29, 2007 |
| A flip-chip ball grid array integrated circuit package with improved thermo-mechanical properties is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. A semiconductor die is flip-chip mounted to the first su |
| 7071545 |
Shielded integrated circuit package |
July 4, 2006 |
| An integrated circuit package is provided. The package includes a die attach pad having a first side and a second side. A first semiconductor die is mounted to the first side of the die attach pad, a plurality of contact pads disposed in close proximity to the first semiconductor die. |
| 7049177 |
Leadless plastic chip carrier with standoff contacts and die attach pad |
May 23, 2006 |
| A process for fabricating a leadless plastic chip carrier includes selectively etching at least a first surface of a leadframe strip to partially define at least a plurality of contact pads and a die attach pad; selectively plating at least one layer of metal on a second surface of t |
| 7033517 |
Method of fabricating a leadless plastic chip carrier |
April 25, 2006 |
| A leadless plastic chip carrier is fabricated by partially etching at least a first surface of a leadframe strip to partially define a die attach pad, a plurality of contact pads disposed around the die attach pad, and a plurality of bond fingers intermediate the die attach pad and t |
| 7009286 |
Thin leadless plastic chip carrier |
March 7, 2006 |
| A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at |
| 6995460 |
Leadless plastic chip carrier with etch back pad singulation |
February 7, 2006 |
| A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, |
| 6989294 |
Leadless plastic chip carrier with etch back pad singulation |
January 24, 2006 |
| A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, |
| 6987032 |
Ball grid array package and process for manufacturing same |
January 17, 2006 |
| A ball grid array package is manufactured by mounting a semiconductor die to a first surface of a substrate and mounting a die adapter to the semiconductor die. The semiconductor die is wire bonded to ones of conductive traces of the substrate. A collapsible spacer is mounted to the |
| 6984785 |
Thermally enhanced cavity-down integrated circuit package |
January 10, 2006 |
| A cavity-down ball grid includes a flexible circuit tape including a flexible tape laminated to a conductor layer. The flexible circuit tape has an aperture therein. A thermally conductive heat spreader is fixed to a first surface of the flexible circuit tape and the heat spreader has a |
| 6982491 |
Sensor semiconductor package and method of manufacturing the same |
January 3, 2006 |
| A process for fabricating an integrated circuit package includes: providing a substrate having conductive traces therein, the substrate including a cavity therein; mounting a semiconductor die to a first surface of the substrate, in a flip-chip orientation such that a sensor portion |
| 6979594 |
Process for manufacturing ball grid array package |
December 27, 2005 |
| A ball grid array package is manufactured by mounting a semiconductor die to a first surface of a substrate array. Wires are bonded between the semiconductor die and ones of conductive traces of the substrate array. The heat spreader is disposed in a mold and the substrate array is r |
| 6964918 |
Electronic components such as thin array plastic packages and process for fabricating same |
November 15, 2005 |
| A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one additional electronic c |
| 6946324 |
Process for fabricating a leadless plastic chip carrier |
September 20, 2005 |
| A process for fabricating a leadless plastic chip carrier includes laminating a first metal strip to a second metal strip to form a leadframe strip, selectively etching the first metal strip to define at least a row of contact pads, mounting a semiconductor die to either a die attach pad |
| 6933594 |
Leadless plastic chip carrier with etch back pad singulation |
August 23, 2005 |
| A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, |
| 6933176 |
Ball grid array package and process for manufacturing same |
August 23, 2005 |
| A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one |
| 6903304 |
Process for dressing molded array package saw blade |
June 7, 2005 |
| A process for reworking or dressing a saw blade used in wafer dicing and singulation of molded array integrated circuit packages, includes rotating the saw blade on a spindle and ablating an edge portion of the saw blade using a laser and thereby dressing the saw blade. |
| 6872661 |
Leadless plastic chip carrier with etch back pad singulation and die attach pad array |
March 29, 2005 |
| A leadless plastic chip carrier has a plurality of die attach pads on which a singulated semi-conductor die is mounted. At least one row of contact pads circumscribes the plurality of die attach pads and a power/ground ring is intermediate the contact pads and the die attach pads. Wire b |
| 6841859 |
Premolded cavity IC package |
January 11, 2005 |
| A process for fabricating a cavity-type integrated circuit package. The process includes: supporting an interior portion of each of a plurality of leads, in a mold; supporting a die attach pad in said mold; molding a package body in said mold such that said leads extend from an interior |
| 6821817 |
Premolded cavity IC package |
November 23, 2004 |
| A process for fabricating a cavity-type integrated circuit package. The process includes: supporting an interior portion of each of a plurality of leads, in a mold; supporting a die attach pad in said mold; molding a package body in said mold such that said leads extend from an interior |
| 6818980 |
Stacked semiconductor package and method of manufacturing the same |
November 16, 2004 |
| An integrated circuit package includes a substrate having conductive traces therein. A first semiconductor die is mounted in a die-down configuration to a first surface of the substrate. A second semiconductor die is mounted to a backside of the first semiconductor die. A plurality of co |
| 6818978 |
Ball grid array package with shielding |
November 16, 2004 |
| An integrated circuit package is provided. The package has a substrate having first and second surfaces and a plurality of conductive traces therebetween. A stacked semiconductor die apparatus is coupled to the substrate. The stacked semiconductor die apparatus includes a first semic |
| 6818472 |
Ball grid array package |
November 16, 2004 |
| An integrated circuit package including a substrate having opposing first and second surfaces. The substrate has conductive traces disposed therein. A semiconductor die is mounted on the first surface of the substrate and a silicon heat sink disposed on a portion of the semiconductor die |
| 6800948 |
Ball grid array package |
October 5, 2004 |
| An integrated circuit package including a substrate having opposing first and second surfaces. The substrate has conductive traces disposed therein. A semiconductor die is mounted on the first surface of the substrate and a silicon heat sink disposed on a portion of the semiconductor die |
| 6781242 |
Thin ball grid array package |
August 24, 2004 |
| An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die i |
| 6737755 |
Ball grid array package with improved thermal characteristics |
May 18, 2004 |
| An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. A semiconductor die is mounted on the first surface of the substrate and an adapter disposed on the semiconductor die. A plurali |
| 6734044 |
Multiple leadframe laminated IC package |
May 11, 2004 |
| A method of fabricating an integrated circuit package. The method includes providing a first leadframe and a second leadframe, laminating the second leadframe to a portion of the first leadframe in order to create a multi-layer laminated leadframe, and mounting a semiconductor die on |
| 6667191 |
Chip scale integrated circuit package |
December 23, 2003 |
| An integrated circuit package including a silicon wafer, a plate of intermetallic compound fixed to the back surface of the silicon wafer and a plurality of solder ball contacts. The solder ball contacts are in electrical connection with die circuitry on the front surface of the sili |
| 6635957 |
Leadless plastic chip carrier with etch back pad singulation and die attach pad array |
October 21, 2003 |
| A leadless plastic chip carrier has a plurality of die attach pads on which a singulated semi-conductor die is mounted. At least one row of contact pads circumscribes the plurality of die attach pads and a power/ground ring is intermediate the contact pads and the die attach pads. Wire b |
| 6586834 |
Die-up tape ball grid array package |
July 1, 2003 |
| An integrated circuit package including a flexible circuit tape having a flexible polyimide tape laminated to a conductor layer, a plurality of blind holes extending through the flexible tape to the conductor layer and a plurality of through holes extending through the flexible tape and |
| 6585905 |
Leadless plastic chip carrier with partial etch die attach pad |
July 1, 2003 |
| A leadless plastic chip carrier comprising a die attach pad, a semiconductor die mounted to a portion of the die attach pad and at least one row of contact pads circumscribing the die attach pad. The row of contact pads have a thickness greater than the thickness of the portion of th |
| 6498099 |
Leadless plastic chip carrier with etch back pad singulation |
December 24, 2002 |
| A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe str |
| 6429048 |
Metal foil laminated IC package |
August 6, 2002 |
| A method of fabricating an integrated circuit package for ball grid arrays, comprising the steps of: laminating layers of fiberglass prepreg and copper foil to a copper plate in order to create a three-layer laminated carrier; patterning and etching contact pads for input/output and a |
| 6294100 |
Exposed die leadless plastic chip carrier |
September 25, 2001 |
| A leadless integrated circuit package, comprising an exposed semiconductor die and contact pads embedded in an over mold, and wires interconnecting the semiconductor die and contact pads. The leadless integrated circuit package is fabricated by etching a leadframe strip to define a plura |
