| Patent Number |
Title Of Patent |
Date Issued |
| 7449922 |
Sensing circuitry and method of detecting a change in voltage on at least one input line |
November 11, 2008 |
| Sensing circuitry and a method of operating such sensing circuitry are provided. The sensing circuitry has voltage change detection circuitry for detecting a change in voltage on at least one input line and for producing at least one output signal indicative of that change during a s |
| 7448050 |
Handling multiple interrupts in a data processing system utilising multiple operating systems |
November 4, 2008 |
| In a data processing system using multiple operating systems, an interrupt which itself may be interrupted by a subsequent interrupt which will be serviced in a different operating system, guards itself against being overlooked when that subsequent interrupt has been handled by starting |
| 7447946 |
Storage of trace data within a data processing apparatus |
November 4, 2008 |
| The present invention provides a data processing apparatus and method for storing trace data. The data processing apparatus comprises a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices. |
| 7447885 |
Reading prediction outcomes within a branch prediction mechanism |
November 4, 2008 |
| A branch prediction mechanism includes a history value register storing a history value which is used to address into a history buffer from which a plurality of prediction values are read and stored into a prediction value store. The one or more prediction values to be used with a po |
| 7447883 |
Allocation of branch target cache resources in dependence upon program instructions within an in |
November 4, 2008 |
| A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10 or both, is used to store branch target addresses or |
| 7447882 |
Context switching within a data processing system having a branch prediction mechanism |
November 4, 2008 |
| A branch target buffer is provided which maintains its entries across context switches within a virtually addressed system. Branch mispredictions are detected for individual entries within the branch target buffer and those individual entries are invalidated. |
| 7447871 |
Data access program instruction encoding |
November 4, 2008 |
| A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilizing a 12-bit offset field but with a fixed addressing mode and a second form utilizing a shorter 8-bit offse |
| 7447726 |
Polynomial and integer multiplication |
November 4, 2008 |
| A method and apparatus for generating a plurality of concurrent significant bits forming at least a portion of a product from at least two partial products, the method comprising the following steps: for each of a plurality of said concurrent predetermined significant bits performing |
| 7447099 |
Leakage mitigation logic |
November 4, 2008 |
| Leakage current from a circuit for handling data is reduced using leakage control circuit operable in a leakage reduction mode. The data handling circuit comprises data handling logic operable to receive an input data value and to output and output data value. The data handling circuit a |
| 7444546 |
On-board diagnostic circuit for an integrated circuit |
October 28, 2008 |
| An integrated circuit having a plurality of functional circuits interconnected via a functional bus is provided with a diagnostic bus-master circuit which uses bus transactions on the functional bus to perform diagnostic operations. These diagnostic operations can be performed in rea |
| 7444271 |
Scoring mechanism for automatically generated test programs |
October 28, 2008 |
| A test program for a data processing apparatus is produced using a genetic algorithm which mutates instances being ordered lists of program instructions within a population forming the test program. The populations are evaluated using a metric by which the population as a whole is sc |
| 7444257 |
Generation of a testbench for a representation of a device |
October 28, 2008 |
| A system and method for generating a testbench for a representation of a device to be incorporated in a data processing apparatus is provided. The representation of the device is configurable based on configuration data specifying predetermined attributes of one or more components of the |
| 7437544 |
Data processing apparatus and method for executing a sequence of instructions including a multip |
October 14, 2008 |
| A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an instruction store for storing the sequence of instructions, and a processing unit for executi |
| 7437400 |
Data processing apparatus and method for performing floating point addition |
October 14, 2008 |
| A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic for determining which of the first and second floating point operands is |
| 7434119 |
Method and apparatus for memory self testing |
October 7, 2008 |
| A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access p |
| 7434072 |
Integrated circuit power management control |
October 7, 2008 |
| Power management control software including power management policies is provided with those policies divided into observation code 18, 20, 22 and response code 26, 28, 30. When predetermined execution points 10, 12 within the operating system 2 are reached registered observation code 18 |
| 7434007 |
Management of cache memories in a data processing apparatus |
October 7, 2008 |
| The present invention provides a data processing apparatus and method for managing cache memories. The data processing apparatus comprises a processing unit for issuing an access request seeking access to a data value, and a hierarchy of cache memories for storing data values for acc |
| 7433911 |
Data processing apparatus and method for performing floating point addition |
October 7, 2008 |
| A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic operable to determine the larger operand of the first and second opera |
| 7428632 |
Branch prediction mechanism using a branch cache memory and an extended pattern cache |
September 23, 2008 |
| A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a plurality of compressed representations of these such that when they recur their termin |
| 7426659 |
Forced diagnostic entry upon power-up |
September 16, 2008 |
| A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the norm |
| 7426629 |
Processing activity masking in a data processing system |
September 16, 2008 |
| A data processing system is provided with mechanisms such that when a data value is stored within a data register, further data values are stored within one or more further registers such that the total number of signal transitions from high to low and from low to high does not vary in |
| 7426320 |
Performance controlling parameter setting in an image processing system |
September 16, 2008 |
| A data processing system is provided for setting a value of a performance controlling parameter during processing of a data stream comprising a plurality of data blocks. The performance controlling parameter is set by deriving a complexity measure for at least one data block by performin |
| 7420970 |
Read ports and methods of outputting data via read ports |
September 2, 2008 |
| A read port for selectively coupling one of a plurality of inputs to an output is disclosed. The read port comprises: a plurality of inputs; an output; a plurality of multiplexers operable to selectively couple a selected input to said output; and a multiplexer control signal input for |
| 7420859 |
Memory device and method of controlling access to such a memory device |
September 2, 2008 |
| The present invention provides a memory device comprising a memory array having a plurality of memory regions, and a plurality of data path access units, each data path access unit being associated with at least one memory region. Each memory region has at least one associated memory |
| 7412633 |
Communication interface for diagnostic circuits of an integrated circuit |
August 12, 2008 |
| An integrated circuit is provided with diagnostic circuitry, such as serial scan chains or debug bus access circuits, with which communication is established using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial |
| 7406585 |
Data processing system having an external instruction set and an internal instruction set |
July 29, 2008 |
| There is provided a system havingan execution core operable to execute internal instructions.A translation buffer is operable to store a plurality of internal instruction blocks of one or more internal instructions where the internal instruction blocks are a dynamic translation of re |
| 7401329 |
Compiling computer programs to exploit parallelism without exceeding available processing resour |
July 15, 2008 |
| A compilation technique for computer programs forms a data flow graph of vertices which are analysed to form clusters C for parallel execution where those clusters are added to up to the point at which arbitrary selection between further vertices C, D to be added must be made. This d |
| 7401273 |
Recovery from errors in a data processing apparatus |
July 15, 2008 |
| A data processing apparatus and method are provided for recovering from errors in the data processing apparatus. The data processing apparatus comprises processing logic operable to perform a data processing operation, and a plurality of sampling circuits, each sampling circuit being |
| 7401210 |
Selecting subroutine return mechanisms |
July 15, 2008 |
| Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect a match and the return instruction response is selected in dependence upon whether or not |
| 7401107 |
Data processing apparatus and method for converting a fixed point number to a floating point num |
July 15, 2008 |
| A data processing apparatus and method are provided for converting an m-bit fixed point number to a rounded floating point number having an n-bit significand, where n is less than m. The data processing apparatus comprises determination logic for determining the bit location of the m |
| 7389459 |
Provision of debug via a separate ring bus in a data processing apparatus |
June 17, 2008 |
| A data processing apparatus is provided having a plurality of functional units. At least one of the functional units is operable to perform data processing operations and at least a subset of the plurality of functional units have at least one of a respective co-processor register fo |
| 7386709 |
Controlling execution of a block of program instructions within a computer processing system |
June 10, 2008 |
| A data processing apparatus is provided with an execute block instruction EMB which specifies a memory location of a block of program instructions to be executed as well as the length of that block of program instructions. When the end of that block of program instructions has been r |
| 7386580 |
Data processing apparatus and method for computing an absolute difference between first and seco |
June 10, 2008 |
| A data processor computes an absolute difference between portions of first and second data elements. At least a part of the first and second data elements are compared to determine which data element is larger. A first comparison result value is produced if the first element is larger an |
| 7383587 |
Exception handling control in a secure processing system |
June 3, 2008 |
| A data processing system includes a processor that can operate in a plurality of modes and in either a secure domain or a non-secure domain. At least one secure mode is a mode in the secure domain, and at least one non-secure mode is a mode in the non-secure domain. When the processor is |
| 7379347 |
Memory device and method for performing write operations in such a memory device |
May 27, 2008 |
| A memory device and method of performing a write operation in such a memory device are provided. The memory device comprises a memory array having a plurality of memory cells, and a plurality of word lines and a plurality of bit lines via which the plurality of memory cells are acces |
| 7373550 |
Generation of a computer program to test for correct operation of a data processing apparatus |
May 13, 2008 |
| Software built in self test computer programs 12 are generated using a genetic algorithm 14 technique. A fault simulator 20 is used to simulate candidate software built in self test computer programs and compare the simulated execution, such to deliberately introduced test faults, with |
| 7370210 |
Apparatus and method for managing processor configuration data |
May 6, 2008 |
| The present invention provides a data processing apparatus and method for managing processor configuration data. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a |
| 7370180 |
Bit field extraction with sign or zero extend |
May 6, 2008 |
| A method of controlling data processing logic which causes a data value to be rotated by a number of bits in order to generate a rotated data value; a number of least significant bits of the rotated data value are masked with other bits of said rotated data value not being masked in orde |
| 7366650 |
Software and hardware simulation |
April 29, 2008 |
| A verification environment is provided that co-verifies a software component 8 and a hardware component 10. Within the same environment using a common test controller 18 both hardware stimuli and software stimuli may be applied to their respective simulators. The response of both the |
| 7363176 |
Operating voltage determination for an integrated circuit |
April 22, 2008 |
| Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vecto |
| 7360061 |
Program instruction decompression and compression techniques |
April 15, 2008 |
| A data processing system including an instruction cache 8 and an instruction decompression circuit 10 between the instruction cache 8 and a compressed instruction data memory 12. The instruction decompression circuit decompresses compressed instruction data CID recovered from the com |
| 7356553 |
Data processing apparatus and method for determining a processing path to perform a data process |
April 8, 2008 |
| The present invention provides a data processing apparatus and method for performing a data processing operation on first and second floating point data elements, the first floating point data element specifying a first exponent and the second floating point data element specifying a sec |
| 7353297 |
Handling of write transactions in a data processing apparatus |
April 1, 2008 |
| A data processing apparatus and method of handling write transactions in such an apparatus is provided. The apparatus has a plurality of devices, and bus circuitry providing connection paths between the plurality of devices. At least one of the devices has a bus master interface operable |
| 7350058 |
Shift and insert instruction for overwriting a subset of data within a register with a shifted r |
March 25, 2008 |
| A data processing system 2 is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that shifted value other than the shifted-in bits into a destination value with the remaining bits |
| 7350055 |
Tightly coupled accelerator |
March 25, 2008 |
| An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values |
| 7350005 |
Handling interrupts in a system having multiple data processing units |
March 25, 2008 |
| An interrupt controller is provided for processing interrupt requests in a system having a plurality of data processing units operable to service those interrupt requests, each interrupt request having an associated priority level. The interrupt controller comprises request logic operabl |
| 7343482 |
Program subgraph identification |
March 11, 2008 |
| There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus |
| 7343481 |
Branch prediction in a data processing system utilizing a cache of previous static predictions |
March 11, 2008 |
| A data processing system incorporates an instruction prefetch unit 8 including a static branch predictor 12. A static branch prediction cache 30, 32, 34 is provided for storing a most recently encountered static branch prediction such that a subsequent request to fetch the already en |
| 7340573 |
Apparatus and method for controlling access to a memory unit |
March 4, 2008 |
| The present invention provides a data processing apparatus and method for controlling access to a memory unit. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a n |
| 7339842 |
Timing control for sense amplifiers in a memory circuit |
March 4, 2008 |
| An integrated circuit 18 includes a memory 20 having timing circuitry formed of a global controller 26 and a self-timing path for triggering the sense amplifiers 28 to read bit lines 30 within the array of bit cells 24. The self timing path includes timing cells 34 embedded within th |
