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Aplus Flash Technology Inc. Patents
Assignee:
Aplus Flash Technology Inc.
Address:
San Jose, CA
No. of patents:
72
Patents:


1 2










Patent Number Title Of Patent Date Issued
RE37419 Flash memory array and decoding architecture October 23, 2001
A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory
8582363 Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory November 12, 2013
A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read op
8295087 Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below October 23, 2012
A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and
8289775 Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cell October 16, 2012
An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing sub-threshold leakage current through unselected nonvolatile memory cells. The apparatus has a
8274829 Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of September 25, 2012
An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdow
8233320 High speed high density NAND-based 2T-NOR flash memory design July 31, 2012
A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS
8149622 Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid April 3, 2012
A memory system includes a NAND flash memory, a NOR flash memory and a SRAM memory on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. Th
8120966 Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory February 21, 2012
A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read op
8120959 NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines February 21, 2012
A nonvolatile memory device includes a nonvolatile memory array including a plurality of charge retaining transistors arranged in rows and columns. The device has a plurality source lines formed in parallel with the bit lines associated with each column. Row decode/driver circuits are
8072811 NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of December 6, 2011
A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR f
7855912 Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile m December 21, 2010
A control apparatus programs, reads, and erases trapped charges representing multiple data bits from a charge trapping region of a NMOS dual-sided charge-trapping nonvolatile memory cell includes a programming circuit, an erasing circuit, and a reading circuit. The programming circui
7830713 Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND fla November 9, 2010
A nonvolatile memory structure with pairs of serially connected select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an
7688612 Bit line structure for a multilevel, dual-sided nonvolatile memory cell array March 30, 2010
A nonvolatile memory array includes a plurality of dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping
7372736 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and div May 13, 2008
A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate
7369438 Combo memory design and technology for multiple-function java card, sim-card, bio-passport and b May 6, 2008
A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that each array may be
7349257 Combination nonvolatile memory using unified technology with byte, page and block write and simu March 25, 2008
A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accom
7339824 Combination nonvolatile memory using unified technology with byte, page and block write and simu March 4, 2008
A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accom
7324384 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and div January 29, 2008
A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with
7289366 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and div October 30, 2007
A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate
7283401 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and div October 16, 2007
A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate
7177190 Combination nonvolatile integrated memory system using a universal technology most suitable for February 13, 2007
A combination EEPROM, NOR-type Flash and NAND-type Flash nonvolatile memory contains memory cells in which a floating gate transistor forms a NAND-type Flash nonvolatile memory cell, forms a NOR-type Flash nonvolatile memory cells and with one or two select transistors forms a two an
7164608 NVRAM memory cell architecture that integrates conventional SRAM and flash cells January 16, 2007
A nonvolatile SRAM array has an array of integrated nonvolatile SRAM circuits arranged in rows and columns on a substrate. Each of the integrated nonvolatile SRAM circuits includes an SRAM cell, a first and second nonvolatile memory element. The SRAM cell has a latched memory element
7154783 Combination nonvolatile memory using unified technology with byte, page and block write and simu December 26, 2006
A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accom
7149120 Combination nonvolatile memory using unified technology with byte, page and block write and simu December 12, 2006
A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accom
7120064 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and div October 10, 2006
A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with
7110302 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and div September 19, 2006
A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with
7102929 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and div September 5, 2006
A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with
7087953 Unified non-volatile memory device and method for integrating NOR and NAND-type flash memory and August 8, 2006
A method for making a unified non-volatile memory (NVM) comprised of a NOR-type flash memory, a NAND-type flash memory, and a 3-transistor EEPROM integrated on the same chip is achieved. This unified NVM can be used in advanced smart card applications. The unification is achieved by
7075826 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and div July 11, 2006
A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with
7064978 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and div June 20, 2006
A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate
6906376 EEPROM cell structure and array architecture June 14, 2005
An EEPROM cell device on a substrate is achieved. The device comprises, first, a selection transistor having gate, drain, source, and channel. The drain is defined as a cell bit line. An isolation transistor has gate, drain, source, and channel. The source is defined as a cell source lin
6891221 Array architecture and process flow of nonvolatile memory devices for mass storage applications May 10, 2005
In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically
6862223 MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIV March 1, 2005
A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FL
6850438 Combination nonvolatile memory using unified technology with byte, page and block write and simu February 1, 2005
A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommoda
6839278 Highly-integrated flash memory and mask ROM array architecture January 4, 2005
A memory device is achieved. The memory device comprises an array of Flash cells and mask ROM cells in a common substrate. Each Flash cell comprises a floating gate, a control gate, a source, a drain, and a channel. Each mask ROM cell comprises a gate, a source, a drain, and a channel. E
6788612 Flash memory array structure suitable for multiple simultaneous operations September 7, 2004
In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained
6788611 Flash memory array structure suitable for multiple simultaneous operations September 7, 2004
In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained
6777292 Set of three level concurrent word line bias conditions for a NOR type flash memory array August 17, 2004
In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second
6757196 Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device June 29, 2004
The present invention describes a two transistor flash EEPROM memory cell which has a symmetrical source and drain structure, which permits the cell size not limited by program and erase operations. The memory cell comprises an NMOS floating gate transistor forming a nonvolatile storage
6717846 Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground co April 6, 2004
In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically
6714457 Parallel channel programming scheme for MLC flash memory March 30, 2004
In the present invention programming a plurality of MLC flash memory cells is done in parallel using a channel programming operation by applying a high positive voltage to a word line and positive voltages to the bit lines connected to cells to be programmed. The positive bit line voltag
6687154 Highly-integrated flash memory and mask ROM array architecture February 3, 2004
A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source li
6660585 Stacked gate flash memory cell with reduced disturb conditions December 9, 2003
In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are
6628563 Flash memory array for multiple simultaneous operations September 30, 2003
A non-volatile integrated circuit memory having an AND-like array structure that is capable of simultaneous reading and writing of digital data to multiple memory cells within the integrated circuit memory has memory cells within an array block of memory cells are arranged in columns and
6620682 Set of three level concurrent word line bias conditions for a nor type flash memory array September 16, 2003
In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second
6584034 Flash memory array structure suitable for multiple simultaneous operations June 24, 2003
In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained
6574152 Circuit design for accepting multiple input voltages for flash EEPROM memory operations June 3, 2003
In the present invention an EEPROM flash memory is operated using the I/O pins of an EPROM. A novel circuit is used that allows a plurality of voltages to be applied at different times to a single pin designated as CEB (chip enable bar) that permits reading and writing of the flash memor
6563742 Method to turn a flash memory into a versatile, low-cost multiple time programmable EPROM May 13, 2003
A multiple time programmable (MTP) memory device is achieved. The device comprises, first, a memory cell array including a means of electrical erasability and electrical programmability. The memory cell array comprises, preferably, a Flash memory cell array. A package has an external
6556481 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory ce April 29, 2003
In the present invention a three step write of a nonvolatile single transistor cell is disclosed. The three steps comprise erasing, reverse programming and programming which can be applied to a plurality of cell types to produce a symmetrical design and allowing shrinkage of the cell
6515910 Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type f February 4, 2003
A method to test the erase condition of memory cells in a memory array device is achieved. The method is further extended to methods to detect and correct under erase and over erase conditions. The erase condition of a section of the memory array device is altered to form an erased secti
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