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Amic Technology, Inc. Patents
Assignee:
Amic Technology, Inc.
Address:
Hsinchu, TW
No. of patents:
13
Patents:












Patent Number Title Of Patent Date Issued
6673652 Underfilling method for a flip-chip packaging process January 6, 2004
An underfilling method for a flip-chip packaging process includes coating a underfill material layer over bumps on a semiconductor substrate, performing a die sawing process on the semiconductor substrate to from a number of dies, and performing a flip-chip process on each of the dies to
6353556 Method for operating non-volatile memory cells March 5, 2002
A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in prepa
6249459 Circuit and method for equalizing erase rate of non-volatile memory cells June 19, 2001
A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in prepa
6219281 System and method for erasing non-volatile memory cells April 17, 2001
A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in prepa
6200828 Integrated circuit package architecture with a variable dispensed compound and method of manufac March 13, 2001
An IC package architecture and a method of manufacturing the same are provided. By this packaging method, a molded compound is first formed, which covers the entire packaging area of the leadframe but leaving a window to expose the area where the chip is to be mounted. After the chip
6198662 Circuit and method for pre-erasing/erasing flash memory array March 6, 2001
A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in prepa
6188604 Flash memory cell & array with improved pre-program and erase characteristics February 13, 2001
A circuit and method for achieving an improved pre-programming of flash memory cells is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for hot electron pre-programming operations. By el
6185133 Flash EPROM using junction hot hole injection for erase February 6, 2001
A novel erase mechanism using junction hot hole injection is disclosed for flash memory cell sector and bulk erase operations. A constant current supply is used so that a suitable junction voltage breakdown can be provided despite expected variations in cell structures, operations, etc.
6166962 Circuit and method for conditioning flash memory array December 26, 2000
A novel cell conditioning mechanism is employed to equalize charge discharge characteristics of flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, and leaves other cells relatively unaffected so that the fast bits are adjusted to have thr
6133067 Architecture for dual-chip integrated circuit package and method of manufacturing the same October 17, 2000
An architecture for a dual-chip IC package and a method of manufacturing the same are provided. The dual-chip IC package allows two chips to be mounted on the same leadframe in the same package. The two chips can be either the same type of a semiconductor device or two different types of
5995418 Circuit and method for erasing flash memory array November 30, 1999
A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operat
5930174 Circuit and method for erasing flash memory array July 27, 1999
A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operat
5912836 Circuit for detecting both charge gain and charge loss properties in a non-volatile memory array June 15, 1999
A test circuit for observing charge retention characteristics of cells in a flash memory array is disclosed. Unlike prior art structures, the present circuit monitors both charge loss and charge gain of cells in the array. In this way, cells having conduction thresholds below a desired t

 
 
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